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@ * # @5 1 %" __gmon_start__ _ITM_deregisterTMCloneTable _ITM_registerTMCloneTable __cxa_finalize drm_intel_bo_alloc drm_intel_bo_alloc_for_render drm_intel_bo_alloc_userptr drm_intel_bo_alloc_tiled drm_intel_bo_reference drm_intel_bo_unreference drm_intel_bo_map drm_intel_bo_unmap drm_intel_bo_subdata drm_intel_bo_get_subdata memcpy drm_intel_bo_wait_rendering drm_intel_bufmgr_destroy drm_intel_bo_exec drm_intel_bo_mrb_exec drm_intel_bufmgr_set_debug drm_intel_bufmgr_check_aperture_space drm_intel_bo_flink drm_intel_bo_emit_reloc drm_intel_bo_emit_reloc_fence drm_intel_bo_pin drm_intel_bo_unpin drm_intel_bo_set_tiling drm_intel_bo_get_tiling drm_intel_bo_set_softpin_offset drm_intel_bo_disable_reuse drm_intel_bo_is_reusable drm_intel_bo_busy drm_intel_bo_madvise drm_intel_bo_use_48b_address_range drm_intel_bo_references drm_intel_get_pipe_from_crtc_id drm_intel_get_aperture_sizes drmIoctl pci_system_init pci_device_find_by_slot pci_device_probe pci_system_cleanup __stack_chk_fail pthread_mutex_lock pthread_mutex_unlock drmMsg __assert_fail drmCommandWriteRead abort calloc ffs malloc pthread_mutex_destroy drmCommandWrite strerror memset __errno_location drm_intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_contended_lock_take drm_intel_bo_fake_alloc_static drm_intel_bo_fake_disable_backing_store drm_intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_init pthread_mutex_init stderr __fprintf_chk munmap drmCloseBufferHandle realloc exit mmap64 ioctl sysconf posix_memalign getpagesize clock_gettime drm_intel_bo_gem_create_from_name drm_intel_gem_bo_map_gtt drm_intel_gem_bo_map_unsynchronized drm_intel_gem_bo_unmap_gtt drm_intel_gem_bo_start_gtt_access drm_intel_gem_bo_wait drm_intel_gem_bo_get_reloc_count drm_intel_gem_bo_clear_relocs drm_intel_gem_bo_aub_dump_bmp drm_intel_gem_bo_context_exec drm_intel_gem_bo_fence_exec drm_intel_bo_gem_create_from_prime drmPrimeFDToHandle lseek64 drm_intel_bo_gem_export_to_prime drmPrimeHandleToFD drm_intel_bufmgr_gem_enable_reuse drm_intel_gem_bo_disable_implicit_sync drm_intel_gem_bo_enable_implicit_sync drm_intel_bufmgr_gem_can_disable_implicit_sync drm_intel_bufmgr_gem_enable_fenced_relocs drm_intel_bufmgr_gem_set_vma_cache_size drm_intel_bufmgr_gem_get_devid drm_intel_bufmgr_gem_set_aub_filename drm_intel_bufmgr_gem_set_aub_dump drm_intel_gem_context_create drm_intel_gem_context_get_id drm_intel_gem_context_destroy drm_intel_get_reset_stats drm_intel_reg_read drm_intel_get_subslice_total drm_intel_get_eu_total drm_intel_get_pooled_eu drm_intel_get_min_eu_in_pool drm_intel_bufmgr_gem_set_aub_annotations drm_intel_gem_bo_map__gtt drm_intel_gem_bo_map__cpu drm_intel_gem_bo_map__wc drm_intel_bufmgr_gem_init geteuid getuid getenv strcmp strtod __sprintf_chk strcat __vfprintf_chk __strcat_chk drm_intel_decode_context_alloc stdout drm_intel_decode_context_free drm_intel_decode_set_dump_past_end drm_intel_decode_set_batch_pointer drm_intel_decode_set_head_tail drm_intel_decode_set_output_file drm_intel_decode fflush libdrm.so.2 libpciaccess.so.0 libc.so.6 _edata __bss_start libdrm_intel.so.1 GLIBC_2.14 GLIBC_2.4 GLIBC_2.17 GLIBC_2.2.5 GLIBC_2.3.4 $ORIGIN/.. O ii
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bo_fake->nr_relocs <= MAX_RELOCS delayed free: offset %x sz %x
return to lru: offset %x sz %x
fence not passed: offset %x sz %x %d %d
%s:%d: Error waiting for fence: %s.
drm_bo_unmap: (buf %d: %s, %lu kb)
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drm_bo_validate: (buf %d: %s, %lu kb)
bo_fake->block->bo == &bo_fake->bo Upload dirty buf %d:%s, sz %lu offset 0x%x
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DRMLISTEMPTY(&bufmgr_fake->on_hardware) drm_fence_validated: 0x%08x cookie
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../intel/intel_bufmgr_fake.c bo_fake->map_count == 0 %s: drm_i915_irq_emit: %d
emit 0x%08x
size != 0 target_bo r->offset != r2->offset block->fenced %s: %d
wait 0x%08x
!(bo_fake->flags & BM_PINNED) set_dirty - buf %d
bo_fake->map_count != 0 free block %p %08x %d %d
- free immediately
!bo_fake->backing_store bo_fake->block == NULL thrashing
%s 0x%lx bytes failed
%s: already mapped
%s: alloc failed
bo_fake->block Failed to validate buf %d:%s
ret == 0 DRM_I915_BATCHBUFFER: %d
drm_intel_fake_bo_alloc drm_intel_fake_bo_unreference_locked drm_intel_fake_emit_reloc drm_intel_bo_fake_post_submit fence_blocks drm_intel_fake_bo_validate alloc_backing_store drm_intel_fake_bo_unmap_locked evict_mru evict_lru evict_and_alloc_block evict_and_alloc_block drm_intel_fake_bo_map_locked drm_intel_fake_bo_map_locked drm_intel_fake_reloc_and_validate_buffer drm_intel_fake_bo_exec drm_intel_bufmgr_fake_evict_all free_backing_store drm_intel_bo_fake_alloc_static set_dirty clear_fenced clear_fenced _fence_emit_internal drm_intel_bufmgr_fake_contended_lock_take ../intel/intel_bufmgr_gem.c offset <= bo->size - 4 !bo_gem->used_as_reloc_target bo_gem->map_count == 0 bo_map: %d (%s) -> %p
bo_map_gtt: %d (%s) -> %p
* %2d: %d %s(%s)
pgsz > 0 alignment == 0 bo_create: buf %d (%s) %ldb
false bo_gem->reloc_count >= start prime map brw INTEL_DEVID_OVERRIDE get chip id failed: %d [%d]
param: %d, val: %d
get fences failed: %d [%d]
g4x ilk snb ivb hsw byt bdw skl kbl bo_gem->reloc_count < bufmgr_gem->max_relocs (write_domain & (write_domain - 1)) == 0 target_bo_gem->reloc_count == 0 check_space: overflowed available aperture, %dkb vs %dkb
drm_check_space: total %dkb vs bufgr %dkb
drmCloseBufferHandle %d failed (%s): %s
%s: cached=%d, open=%d, limit=%d
bo_map: %d (%s), map_count=%d
%s:%d: Error mapping buffer %d (%s): %s .
%s:%d: Error setting to CPU domain %d: %s
bo_map_gtt: mmap %d (%s), map_count=%d
%s:%d: Error preparing buffer map %d (%s): %s .
Execbuffer fails to pin. Estimate: %u. Actual: %u. Available: %u
!(bo_gem->kflags & EXEC_OBJECT_PINNED) BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x
%2d: %d %s(%s)@0x%08x %08x -> %d (%s)@0x%08x %08x + 0x%08x
%2d: %d %s(%s) -> %d *(%s)@0x%08x %08x
Failed to get a page (%ld) for userptr detection!
bo_create_userptr: ioctl failed with user ptr %p size 0x%lx, user flags 0x%lx
bo_create_userptr: ptr %p buf %d (%s) size %ldb, stride 0x%x, tile mode %d
attempted to unmap an unmapped bo
i < ARRAY_SIZE(bufmgr_gem->cache_bucket) atomic_read(&bo_gem->refcount) > 0 bo_unreference final: %d (%s)
bo freed with non-zero map-count %d
Failed to release test userptr object! (%d) i915 kernel driver may not be sane!
Couldn't reference %s handle 0x%08x: %s
bo_create_from_handle: %d (%s)
%s:%d: Error setting domain %d: %s
%s:%d: Error setting memory domains %d (%08x %08x): %s .
%s:%d: Timed wait is not supported. Falling back to infinite wait
create_from_prime: failed to obtain handle from fd: %s
libdrm aub dumping is deprecated.
Use intel_aubdump from intel-gpu-tools instead. Install intel-gpu-tools,
then run (for example)
$ intel_aubdump --output=trace.aub glxgears -geometry 500x500
See the intel_aubdump man page for more details.
DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s
DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s
%s:%d: Error reading data from buffer %d: (%d %d) %s .
%s:%d: Error writing data to buffer %d: (%d %d) %s .
DRM_IOCTL_I915_GEM_APERTURE failed: %s
Assuming %dkB available aperture size.
May lead to reduced performance or incorrect rendering.
i915 does not support EXECBUFER2
add_bucket has_userptr drm_intel_gem_bo_alloc_internal drm_intel_gem_bo_unreference mmap_write set_domain is_cache_coherent mmap_read do_bo_emit_reloc drm_intel_update_buffer_offsets2 drm_intel_gem_bo_unreference_locked_timed drm_intel_gem_bo_clear_relocs drm_intel_gem_bo_purge_vma_cache drm_intel_gem_bo_purge_vma_cache drm_intel_bo_gem_set_in_aperture_size -bad -1 -0 -w -z -y -x always never less lequal greater notequal gequal keep zero replace incr_sat decr_sat incr decr inv_src_colr inv_src_alpha inv_dst_alpha inv_dst_colr src_alpha_sat inv_cnst_colr cnst_alpha inv_const_alpha point list line list line strip tri list tri strip tri fan quad list quad strip line list adj line strip adj tri list adj tri strip adj tri strip reverse polygon rect list line loop point list bf line strip cont line strip bf line strip cont bf tri fan no stipple fail .sat R%d%s%s bad destination reg oC%d
oC%s%s bad destination reg oD%d
oD%s%s bad destination reg U%d
U%d%s%s R%d bad src reg %s
T%d bad src reg T%d
C%d bad src reg oC%d
bad src reg oD%d
U%d bad src reg type %d
.%s%s%s%s .xyzw TAIL 0x%08x: %s 0x%08x: %s use compare reg compare semaphore, update semaphore, global gtt, use per-process HWS, no write write data reserved write TIMESTAMP enable notify interrupt, flush gfdt, invalidate tlb, store in hws, MI_ARB_ON_OFF MI_BATCH_BUFFER_END MI_BATCH_BUFFER MI_BATCH_BUFFER_START MI_DISPLAY_BUFFER_INFO MI_FLUSH MI_LOAD_REGISTER_IMM MI_LOAD_SCAN_LINES_EXCL MI_LOAD_SCAN_LINES_INCL MI_NOOP MI_OVERLAY_FLIP MI_REPORT_HEAD MI_SET_CONTEXT MI_STORE_DATA_IMM MI_STORE_DATA_INDEX MI_STORE_REGISTER_MEM MI_USER_INTERRUPT MI_WAIT_FOR_EVENT MI_SEMAPHORE_MBOX MI_FLUSH_DW MI_REPORT_PERF_COUNT MI_LOAD_REGISTER_MEM MI_SUSPEND_FLUSH MI_BATCH_BUFFER_END
MI_SEMAPHORE_MBOX%s%s%s%s %u
value
MI_STORE_DATA_INDEX%s
upper dword
MI_NOOP
hws index
dword %d
MI UNKNOWN
, cc wait 1 , plane A scan line wait , plane A pending flip wait , pipe A vblank wait , fbc idle wait , pipe B scan line wait , plane B pending flip wait , pipe B vblank wait , plane C pending flip wait , pipe A hblank wait , pipe B hblank wait , overlay flip pending wait , pipe A start vblank wait , pipe B start vblank wait , sprite A pending flip wait , plane B scan line wait , sprite B pending flip wait , sprite C pending flip wait , cc wait 4 , cc wait 3 , cc wait 2 , Restore Inhibit , Force Restore MI_SET_CONTEXT
gtt offset = 0x%x%s%s
en dis solid pattern enabled, dest (%d,%d)
XY_SETUP_BLT Bad count in XY_SETUP_BLT
cliprect (%d,%d)
setup dst offset 0x%08x
setup background color
setup foreground color
color pattern offset
XY_SETUP_CLIP_BLT XY_SETUP_MONO_PATTERN_SL_BLT mono pattern dw0
mono pattern dw1
XY_COLOR_BLT Bad count in XY_COLOR_BLT
XY_SRC_COPY_BLT Bad count in XY_SRC_COPY_BLT
dst (%d,%d)
src (%d,%d)
src pitch %d
src offset 0x%08x
Bad count in %s
2D UNKNOWN
XY_PIXEL_BLT XY_SCANLINES_BLT Y_TEXT_BLT XY_TEXT_IMMEDIATE_BLT XY_PAT_BLT XY_PAT_CHROMA_BLT XY_PAT_BLT_IMMEDIATE XY_PAT_CHROMA_BLT_IMMEDIATE XY_MONO_PAT_BLT XY_MONO_PAT_FIXED_BLT XY_MONO_SRC_COPY_BLT XY_FULL_BLT XY_FULL_IMMEDIATE_PATTERN_BLT XY_FULL_MONO_SRC_BLT XY_FULL_MONO_PATTERN_BLT random sequential 3DPRIMITIVE: %s %s
vertex count
start vertex
instance count
start instance
index bias
predicated ignored 3DPRIMITIVE: %s%s
3DSTATE_URB_%s
unchanged 3DSTATE_BLEND_STATE_POINTERS
pointer to CC viewport
pointer to SF_CLIP viewport
3DSTATE_CONSTANT_%s
len 0 = %d, len 1 = %d
len 2 = %d, len 3 = %d
pointer to constbuf 0
pointer to constbuf 1
pointer to constbuf 2
pointer to constbuf 3
3DSTATE_WM
kernel start pointer 0
scratch offset
kernel start pointer 1
kernel start pointer 2
computed depth <= computed depth computed depth >= , ZW sample , BAD ZW interp , ZW centroid , point UL , point UR , line stipple , poly stipple , coverage , source W , source depth , kill , hiz resolve , depth resolve , disabled , depth clear NPS NPC NPP MS
3DSTATE_CC_STATE_POINTERS
blend change %d
depth stencil change %d
cc change %d
3DSTATE_HIER_DEPTH_BUFFER
pointer to HiZ buffer
%s state base address 0x%08x
%s state base not updated
%s state upper bound 0x%08x
TRILIST TRISTRIP TRISTRIP_REVERSE TRIFAN POLYGON LINELIST LINESTRIP RECTLIST POINTLIST DIB CLEAR_RECT unknown 3DPRIMITIVE inline %s
3DPRIMITIVE inline unknown vertex format
V%d.X = %f
V%d.Y = %f
missing data in V%d
V%d.Z = %f
V%d.W = %f
bad S4 position mask
V%d.width = 0x%08x)
V%d.T%d.X = %f
V%d.T%d.Y = %f
V%d.T%d.Z = %f
V%d.T%d.W = %f
bad S2.T%d format
3DPRIMITIVE random indirect indices: (terminator)
indices: 0x%04x, 0x%04x
indices: 0x%04x
start
%s: %s %s, %s, %s, %s
%s: %s %s, %s
%s: %s %s, %s, %s
%s: %s %s, S%d, %s
ccw both none XYZ, XYZW, XY, XYW, XYZF, XYZWF, XYF, XYWF, line AA enable, point sprite enable, local depth ofs enable, force default specular, force default diffuse, FogParam, DepthOfs, Color, SpecFog, PointWidth, Specular, Alpha, flatshade= logicop enable, color dither enable, stencil test enable, stencil write enable, fog enable, global depth ofs enable, last pixel enable, force default point size, Blue, Green, Red, write_disable= cbuf write enable, depth write enable, cbuf blend enable, alpha test enable, use fence x-tiled y-tiled vertical ofs enable, vertical line stride enable, untrusted surface, BAD 8b I 16b rgb565 32b argb8888 422 yuv_swapy compressed dxt1 4b indexed mono bump655 ay88 argb4444 argb1555 xL824 xA824 xI824 vu1616 gr1616 awvu2101010 abgr2101010 argb2101010 xlvu8888 lxvu8888 axvu8888 qwvu8888 xbgr8888 xrgb8888 abgr8888 yuv_swapuvy yuv_swapuv yuv dxt1_rb fxt1 dxt4_5 dxt2_3 palette select miplayout legacy miplayout right 2D CUBE RESERVED nearest linear shadow, anisotropic 4x4_1 4x4_2 4x4_flat 6x5_mono colorspace conversion, packed2planar, reverse gamma, deinterlacer, normalized coords, wrap mirror clamp_edge cube clamp_border mirror_once kill pixel enable, g8 x1r5g5b5 r5g6b5 a8r8g8b8 ycrcb_swapy ycrcb_normal ycrcb_swapuv ycrcb_swapuvy a4r4g4b4 a1r5g5b5 a2r10g10b10 u16 f16 u24x8 color depth ofs disabled stencil, depth, color, ZONE_INIT 3DSTATE_LOAD_INDIRECT
SIS.0
SIS.1
DIS.0
SSB.0
SSB.1
MSB.0
MSB.1
PSP.0
PSP.1
PSC.0
PSC.1
S0: vbo offset: 0x%08x%s
S2: texcoord formats: %i=2D %i=3D %i=4D %i=1D %i=2D_16 %i=4D_16 %i=NP S3: not documented
S%d: 0x%08x
TBCF
TB%dC
TB%dA
TM%dS0: offset=0x%08x, %s
TM%dS2: pitch=%i,
TM%dS3
TM%dS4: dflt color
3DSTATE_MAP_STATE
map %d MS2 %s%s%s
C%d.X = %f
C%d.Y = %f
C%d.Z = %f
C%d.W = %f
3DSTATE_PIXEL_SHADER_PROGRAM
PS%03d %s: NOP
MOV MUL MAD DP2ADD DP3 DP4 FRC RCP RSQ EXP LOG CMP MIN MAX FLR MOD TRC SGE SLT TEXLD TEXLDP TEXLDB . bad (empty) dcl mask
bad T%d dcl register number
.x .xy .xz .w bad T%d.%s dcl mask
%s: DCL T%d%s
errataed bad dcl mask %s
.xw .xzw %s: DCL DIFFUSE%s
%s: DCL SPECULAR%s
%s: DCL FOG%s
%s: DCL S%d %s
%s: DCL RESERVED%d
%s: unknown
3DSTATE_SAMPLER_STATE
sampler %d SS4: border color
3DSTATE_BUFFER_INFO
%s, tiling = %s, pitch=%d
3DSTATE_SCISSOR_RECTANGLE
3DSTATE_DRAWING_RECTANGLE
3DSTATE_CLEAR_PARAMETERS
prim_type=%s, clear=%s%s%s
clear color
clear depth/stencil
color value (rgba8888)
depth value %f
clear stencil
3DSTATE_CHROMA_KEY 3DSTATE_CONSTANT_BLEND_COLOR 3DSTATE_DEFAULT_DIFFUSE 3DSTATE_DEFAULT_SPECULAR 3DSTATE_DEFAULT_Z 3DSTATE_DEPTH_OFFSET_SCALE 3DSTATE_MONO_FILTER 3DSTATE_FOG_MODE 3DSTATE_MAP_PALLETE_LOAD_32 3DSTATE_SPAN_STIPPLE 3DSTATE_W_STATE_I830 3DSTATE_COLOR_FACTOR_I830 enabled 3DSTATE_SCISSOR_ENABLE %s
3DSTATE_MAP_COORD_SET_I830
3DSTATE_MAP_CUBE_I830
3DSTATE_MAP_TEX_STREAM_I830
3DSTATE_MODES_3 3DSTATE_ENABLES_1 3DSTATE_ENABLES_2 3DSTATE_VFT0 3DSTATE_AA 3DSTATE_RASTERIZATION_RULES 3DSTATE_MODES_1 3DSTATE_STENCIL_TEST 3DSTATE_VFT1 3DSTATE_INDPT_ALPHA_BLEND 3DSTATE_MODES_5 3DSTATE_MAP_BLEND_OP 3DSTATE_MAP_BLEND_ARG 3DSTATE_MODES_2 3DSTATE_FOG_COLOR 3DSTATE_MODES_4 nostore 1.0 0x1 VID 0.0 vs gs clip sf vfe cs invalid in D3D OGL CCW not s8_z24float z32float z24s8 z16 1D TIMESTAMP write qword write PS_DEPTH_COUNT write depth cache flush, stall at scoreboard, state cache invalidate, constant cache invalidate, vf fetch invalidate, DC flush, protect mem app_id, PIPE_CONTROL flush, notify irq, indirect state invalidate, texture cache invalidate, render target cache flush, depth stall, media state clear, gfdt flush, tlb invalidate, global snapshot count reset, cs stall, no URB_FENCE CS_URB_STATE CONSTANT_BUFFER STATE_BASE_ADDRESS STATE_SIP 3DSTATE_PIPELINE_SELECT 3DSTATE_VF_STATISTICS 3DSTATE_PIPELINED_POINTERS 3DSTATE_DEPTH_BUFFER 3DSTATE_URB 3DSTATE_CLEAR_PARAMS 3DSTATE_STENCIL_BUFFER 3DSTATE_HIER_DEPTH_BUFFER 3DSTATE_VERTEX_BUFFERS 3DSTATE_VERTEX_ELEMENTS 3DSTATE_INDEX_BUFFER 3DSTATE_SCISSOR_POINTERS 3DSTATE_VS 3DSTATE_GS 3DSTATE_CLIP 3DSTATE_SF 3DSTATE_WM 3DSTATE_CONSTANT_VS_STATE 3DSTATE_CONSTANT_VS 3DSTATE_CONSTANT_GS_STATE 3DSTATE_CONSTANT_GS 3DSTATE_CONSTANT_PS_STATE 3DSTATE_CONSTANT_PS 3DSTATE_SAMPLE_MASK 3DSTATE_CONSTANT_HS 3DSTATE_CONSTANT_DS 3DSTATE_HS 3DSTATE_TE 3DSTATE_DS 3DSTATE_STREAMOUT 3DSTATE_SBE 3DSTATE_PS 3DSTATE_DRAWING_RECTANGLE 3DSTATE_CONSTANT_COLOR 3DSTATE_POLY_STIPPLE_OFFSET 3DSTATE_POLY_STIPPLE_PATTERN 3DSTATE_LINE_STIPPLE 3DSTATE_AA_LINE_PARAMETERS 3DSTATE_GS_SVB_INDEX 3DSTATE_MULTISAMPLE 3DSTATE_SO_DECL_LIST 3DSTATE_SO_BUFFER PIPE_CONTROL Bad count in URB_FENCE
URB_FENCE: %s%s%s%s%s%s
gs fence < vs fence!
clip fence < gs fence!
sf fence < clip fence!
cs fence < sf fence!
CS_URB_STATE
CONSTANT_BUFFER: %s
STATE_BASE_ADDRESS
dynamic instruction general 3DSTATE_PIPELINED_POINTERS
VS state
GS state
Clip state
SF state
WM state
CC state
VS binding table
GS binding table
Clip binding table
SF binding table
WM binding table
VS sampler state
GS sampler state
WM sampler state
3DSTATE_URB
3DSTATE_VERTEX_BUFFERS
buffer %d: %s, pitch %db
max index
mbz
3DSTATE_VERTEX_ELEMENTS
clip
sf
cc
3DSTATE_INDEX_BUFFER
beginning buffer address
ending buffer address
3DSTATE_SCISSOR_POINTERS
scissor rect offset
3DSTATE_VS
kernel pointer
3DSTATE_GS
3DSTATE_CLIP
3DSTATE_SF
Global Depth Offset Scale %f
Global Depth Offset Clamp %f
Point Sprite TexCoord Enable
Const Interp Enable
top left: %d,%d
bottom right: %d,%d
origin: %d,%d
3DSTATE_DEPTH_BUFFER
depth offset
%dx%d
volume depth
render target view extent
Bad count in PIPE_CONTROL
destination address
immediate dword low
immediate dword high
surface 3DSTATE_ANTI_ALIASING 3DSTATE_BACKFACE_STENCIL_OPS 3DSTATE_COORD_SET_BINDINGS 3D UNKNOWN: 3d opcode = 0x%x
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heap == 0
Free list:
End of memory blocks
p->free block already free
block is reserved
Offset:%08x, Size:%08x, %c%c
FREE Offset:%08x, Size:%08x, %c%c
Join2Blocks mmAllocMem ; ,M, PT Tl T T U ,U B* B B F & J j N .
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