/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/linux/mfd/
/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/linux/mfd
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abx500/-0755rm
arizona/-0755rm
da9052/-0755rm
da9055/-0755rm
da9062/-0755rm
da9063/-0755rm
da9150/-0755rm
mt6323/-0755rm
mt6397/-0755rm
pcf50633/-0755rm
samsung/-0755rm
syscon/-0755rm
wm831x/-0755rm
wm8350/-0755rm
wm8994/-0755rm
88pm80x.h102260644editdlrm
88pm860x.h136540644editdlrm
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ac100.h62670644editdlrm
adp5520.h84990644editdlrm
altera-a10sr.h35070644editdlrm
as3711.h29600644editdlrm
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asic3.h125140644editdlrm
atmel-hlcdc.h26340644editdlrm
axp20x.h172140644editdlrm
bcm590xx.h8310644editdlrm
bd9571mwv.h37120644editdlrm
core.h47940644editdlrm
cros_ec.h105950644editdlrm
cros_ec_commands.h875080644editdlrm
cros_ec_lpc_mec.h28380644editdlrm
cros_ec_lpc_reg.h19490644editdlrm
da8xx-cfgchip.h75010644editdlrm
da903x.h72180644editdlrm
davinci_voicecodec.h33230644editdlrm
db8500-prcmu.h222050644editdlrm
dbx500-prcmu.h146810644editdlrm
dln2.h36170644editdlrm
dm355evm_msp.h28790644editdlrm
ds1wm.h8170644editdlrm
ezx-pcap.h79320644editdlrm
hi655x-pmic.h20760644editdlrm
hi6421-pmic.h13290644editdlrm
htc-pasic3.h12250644editdlrm
imx25-tsadc.h49720644editdlrm
intel_msic.h163760644editdlrm
intel_soc_pmic.h12650644editdlrm
intel_soc_pmic_bxtwc.h20530644editdlrm
ipaq-micro.h37500644editdlrm
janz.h10530644editdlrm
kempld.h42600644editdlrm
lm3533.h26500644editdlrm
lochnagar.h16240644editdlrm
lochnagar1_regs.h78960644editdlrm
lochnagar2_regs.h155500644editdlrm
lp873x.h88950644editdlrm
lp3943.h27470644editdlrm
lp8788-isink.h12180644editdlrm
lp8788.h85730644editdlrm
lp87565.h78620644editdlrm
lpc_ich.h12610644editdlrm
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max8997-private.h127330644editdlrm
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max77693-common.h13030644editdlrm
max77693-private.h183840644editdlrm
max77693.h22950644editdlrm
max77843-private.h158040644editdlrm
mc13xxx.h78720644editdlrm
mc13783.h29020644editdlrm
mc13892.h9380644editdlrm
mcp.h18160644editdlrm
menelaus.h12840644editdlrm
motorola-cpcap.h127970644editdlrm
mxs-lradc.h61910644editdlrm
palmas.h1526450644editdlrm
qcom_rpm.h2930644editdlrm
rave-sp.h14140644editdlrm
rc5t583.h100560644editdlrm
rdc321x.h5910644editdlrm
retu.h7230644editdlrm
rk808.h128070644editdlrm
rn5t618.h75190644editdlrm
rt5033-private.h80260644editdlrm
rt5033.h12430644editdlrm
si476x-core.h156060644editdlrm
si476x-platform.h66030644editdlrm
si476x-reports.h50100644editdlrm
sky81452.h9900644editdlrm
smsc.h29210644editdlrm
sta2x11-mfd.h191690644editdlrm
stm32-lptimer.h18170644editdlrm
stm32-timers.h57840644editdlrm
stmpe.h34660644editdlrm
stw481x.h14420644editdlrm
sun4i-gpadc.h37100644editdlrm
syscon.h14430644editdlrm
t7l66xb.h8170644editdlrm
tc3589x.h39990644editdlrm
tc6387xb.h5160644editdlrm
tc6393xb.h15480644editdlrm
ti-lmu-register.h76130644editdlrm
ti-lmu.h18220644editdlrm
ti_am335x_tscadc.h58610644editdlrm
tmio.h40980644editdlrm
tps6105x.h30990644editdlrm
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twl.h261890644editdlrm
twl4030-audio.h87410644editdlrm
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ucb1x00.h67280644editdlrm
viperboard.h30220644editdlrm
wl1273-core.h84960644editdlrm
wm97xx.h5760644editdlrm
wm8400-audio.h714710644editdlrm
wm8400-private.h593760644editdlrm
wm8400.h12130644editdlrm
Edit: /usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/linux/mfd/da8xx-cfgchip.h (7501B)
/* * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers. * * Copyright (C) 2016 David Lechner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef __LINUX_MFD_DA8XX_CFGCHIP_H #define __LINUX_MFD_DA8XX_CFGCHIP_H #include /* register offset (32-bit registers) */ #define CFGCHIP(n) ((n) * 4) /* CFGCHIP0 (PLL0/EDMA3_0) register bits */ #define CFGCHIP0_PLL_MASTER_LOCK BIT(4) #define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2) #define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3) #define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0) #define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1) #define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2) #define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0) #define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3) #define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0) #define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1) #define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2) /* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */ #define CFGCHIP1_CAP2SRC(n) ((n) << 27) #define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f) #define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0) #define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1) #define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2) #define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7) #define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8) #define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9) #define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa) #define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb) #define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc) #define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd) #define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe) #define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf) #define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10) #define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11) #define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12) #define CFGCHIP1_CAP1SRC(n) ((n) << 22) #define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f) #define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0) #define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1) #define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2) #define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7) #define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8) #define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9) #define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa) #define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb) #define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc) #define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd) #define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe) #define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf) #define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10) #define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11) #define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12) #define CFGCHIP1_CAP0SRC(n) ((n) << 17) #define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f) #define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0) #define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1) #define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2) #define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7) #define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8) #define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9) #define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa) #define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb) #define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc) #define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd) #define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe) #define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf) #define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10) #define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11) #define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12) #define CFGCHIP1_HPIBYTEAD BIT(16) #define CFGCHIP1_HPIENA BIT(15) #define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13) #define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3) #define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0) #define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1) #define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2) #define CFGCHIP1_TBCLKSYNC BIT(12) #define CFGCHIP1_AMUTESEL0(n) ((n) << 0) #define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf) #define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0) #define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1) #define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2) #define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3) #define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4) #define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5) #define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6) #define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7) #define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8) /* CFGCHIP2 (USB PHY) register bits */ #define CFGCHIP2_PHYCLKGD BIT(17) #define CFGCHIP2_VBUSSENSE BIT(16) #define CFGCHIP2_RESET BIT(15) #define CFGCHIP2_OTGMODE(n) ((n) << 13) #define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3) #define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0) #define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1) #define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2) #define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3) #define CFGCHIP2_USB1PHYCLKMUX BIT(12) #define CFGCHIP2_USB2PHYCLKMUX BIT(11) #define CFGCHIP2_PHYPWRDN BIT(10) #define CFGCHIP2_OTGPWRDN BIT(9) #define CFGCHIP2_DATPOL BIT(8) #define CFGCHIP2_USB1SUSPENDM BIT(7) #define CFGCHIP2_PHY_PLLON BIT(6) #define CFGCHIP2_SESENDEN BIT(5) #define CFGCHIP2_VBDTCTEN BIT(4) #define CFGCHIP2_REFFREQ(n) ((n) << 0) #define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf) #define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1) #define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2) #define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3) #define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4) #define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5) #define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6) #define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7) #define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8) #define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9) /* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */ #define CFGCHIP3_RMII_SEL BIT(8) #define CFGCHIP3_UPP_TX_CLKSRC BIT(6) #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5) #define CFGCHIP3_ASYNC3_CLKSRC BIT(4) #define CFGCHIP3_PRUEVTSEL BIT(3) #define CFGCHIP3_DIV45PENA BIT(2) #define CFGCHIP3_EMA_CLKSRC BIT(1) /* CFGCHIP4 (McASP0 AMUNTEIN) register bits */ #define CFGCHIP4_AMUTECLR0 BIT(0) #endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */