Name	Size	Mode	Actions
ipc4/	-	0755	rm
channel_map.h	2011	0644	editdlrm
control.h	5037	0644	editdlrm
dai-amd.h	770	0644	editdlrm
dai-imx.h	1243	0644	editdlrm
dai-intel.h	7376	0644	editdlrm
dai-mediatek.h	479	0644	editdlrm
dai.h	4796	0644	editdlrm
debug.h	1466	0644	editdlrm
ext_manifest.h	3804	0644	editdlrm
ext_manifest4.h	3593	0644	editdlrm
header.h	6944	0644	editdlrm
info.h	3636	0644	editdlrm
pm.h	1173	0644	editdlrm
stream.h	4701	0644	editdlrm
topology.h	8728	0644	editdlrm
trace.h	3550	0644	editdlrm
xtensa.h	1032	0644	editdlrm

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* * Copyright 2019 NXP * * Author: Daniel Baluta */ #ifndef __INCLUDE_SOUND_SOF_DAI_IMX_H__ #define __INCLUDE_SOUND_SOF_DAI_IMX_H__ #include /* ESAI Configuration Request - SOF_IPC_DAI_ESAI_CONFIG */ struct sof_ipc_dai_esai_params { struct sof_ipc_hdr hdr; /* MCLK */ uint16_t reserved1; uint16_t mclk_id; uint32_t mclk_direction; uint32_t mclk_rate; /* MCLK frequency in Hz */ uint32_t fsync_rate; /* FSYNC frequency in Hz */ uint32_t bclk_rate; /* BCLK frequency in Hz */ /* TDM */ uint32_t tdm_slots; uint32_t rx_slots; uint32_t tx_slots; uint16_t tdm_slot_width; uint16_t reserved2; /* alignment */ } __packed; /* SAI Configuration Request - SOF_IPC_DAI_SAI_CONFIG */ struct sof_ipc_dai_sai_params { struct sof_ipc_hdr hdr; /* MCLK */ uint16_t reserved1; uint16_t mclk_id; uint32_t mclk_direction; uint32_t mclk_rate; /* MCLK frequency in Hz */ uint32_t fsync_rate; /* FSYNC frequency in Hz */ uint32_t bclk_rate; /* BCLK frequency in Hz */ /* TDM */ uint32_t tdm_slots; uint32_t rx_slots; uint32_t tx_slots; uint16_t tdm_slot_width; uint16_t reserved2; /* alignment */ } __packed; #endif