FM / asm

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/arch/x86/include/asm/

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/arch/x86/include/asm

Name	Size	Mode	Actions
crypto/	-	0755	rm
e820/	-	0755	rm
fpu/	-	0755	rm
numachip/	-	0755	rm
shared/	-	0755	rm
trace/	-	0755	rm
uv/	-	0755	rm
vdso/	-	0755	rm
xen/	-	0755	rm
a.out-core.h	1931	0644	edit dl rm
acenv.h	1596	0644	edit dl rm
acpi.h	5300	0644	edit dl rm
agp.h	1070	0644	edit dl rm
alternative.h	11407	0644	edit dl rm
amd-ibs.h	5020	0644	edit dl rm
amd_hsmp.h	364	0644	edit dl rm
amd_nb.h	3086	0644	edit dl rm
apb_timer.h	1466	0644	edit dl rm
apic.h	14661	0644	edit dl rm
apicdef.h	11565	0644	edit dl rm
apic_flat_64.h	151	0644	edit dl rm
apm.h	1768	0644	edit dl rm
archrandom.h	3221	0644	edit dl rm
arch_hweight.h	1311	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	946	0644	edit dl rm
asm.h	5186	0644	edit dl rm
atomic.h	6279	0644	edit dl rm
atomic64_32.h	8150	0644	edit dl rm
atomic64_64.h	5933	0644	edit dl rm
audit.h	170	0644	edit dl rm
barrier.h	2471	0644	edit dl rm
bios_ebda.h	914	0644	edit dl rm
bitops.h	10727	0644	edit dl rm
boot.h	1825	0644	edit dl rm
bootparam_utils.h	2907	0644	edit dl rm
bug.h	2117	0644	edit dl rm
bugs.h	533	0644	edit dl rm
cache.h	641	0644	edit dl rm
cacheflush.h	306	0644	edit dl rm
cacheinfo.h	209	0644	edit dl rm
calgary.h	2370	0644	edit dl rm
ce4100.h	121	0644	edit dl rm
checksum.h	133	0644	edit dl rm
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checksum_64.h	5541	0644	edit dl rm
clocksource.h	480	0644	edit dl rm
cmdline.h	302	0644	edit dl rm
cmpxchg.h	7891	0644	edit dl rm
cmpxchg_32.h	3247	0644	edit dl rm
cmpxchg_64.h	552	0644	edit dl rm
coco.h	482	0644	edit dl rm
compat.h	4861	0644	edit dl rm
cpu.h	2607	0644	edit dl rm
cpufeature.h	9470	0644	edit dl rm
cpufeatures.h	32845	0644	edit dl rm
cpuid.h	498	0644	edit dl rm
cpuidle_haltpoll.h	189	0644	edit dl rm
cpumask.h	408	0644	edit dl rm
cpu_device_id.h	8109	0644	edit dl rm
cpu_entry_area.h	4162	0644	edit dl rm
crash.h	300	0644	edit dl rm
current.h	443	0644	edit dl rm
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delay.h	275	0644	edit dl rm
desc.h	12274	0644	edit dl rm
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device.h	328	0644	edit dl rm
disabled-features.h	3559	0644	edit dl rm
div64.h	2189	0644	edit dl rm
dma-mapping.h	288	0644	edit dl rm
dma.h	9827	0644	edit dl rm
dmi.h	556	0644	edit dl rm
dwarf2.h	2487	0644	edit dl rm
edac.h	474	0644	edit dl rm
efi.h	7416	0644	edit dl rm
elf.h	12640	0644	edit dl rm
emergency-restart.h	202	0644	edit dl rm
emulate_prefix.h	484	0644	edit dl rm
enclu.h	181	0644	edit dl rm
entry_arch.h	1922	0644	edit dl rm
espfix.h	426	0644	edit dl rm
exec.h	37	0644	edit dl rm
export.h	120	0644	edit dl rm
extable.h	1300	0644	edit dl rm
fb.h	540	0644	edit dl rm
fixmap.h	6381	0644	edit dl rm
floppy.h	6748	0644	edit dl rm
frame.h	2237	0644	edit dl rm
fsgsbase.h	2072	0644	edit dl rm
ftrace.h	2777	0644	edit dl rm
futex.h	2269	0644	edit dl rm
gart.h	2682	0644	edit dl rm
genapic.h	22	0644	edit dl rm
geode.h	842	0644	edit dl rm
hardirq.h	2207	0644	edit dl rm
highmem.h	2466	0644	edit dl rm
hpet.h	3461	0644	edit dl rm
hugetlb.h	1867	0644	edit dl rm
hw_breakpoint.h	2112	0644	edit dl rm
hw_irq.h	4126	0644	edit dl rm
hyperv-tlfs.h	22337	0644	edit dl rm
hypervisor.h	1975	0644	edit dl rm
i8259.h	1975	0644	edit dl rm
ia32.h	1789	0644	edit dl rm
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imr.h	1849	0644	edit dl rm
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init.h	632	0644	edit dl rm
insn-eval.h	1546	0644	edit dl rm
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inst.h	5453	0644	edit dl rm
intel-family.h	5168	0644	edit dl rm
intel-mid.h	5025	0644	edit dl rm
intel_ds.h	849	0644	edit dl rm
intel_mid_vrtc.h	330	0644	edit dl rm
intel_pconfig.h	1545	0644	edit dl rm
intel_pmc_ipc.h	2267	0644	edit dl rm
intel_pt.h	1276	0644	edit dl rm
intel_punit_ipc.h	4666	0644	edit dl rm
intel_scu_ipc.h	2351	0644	edit dl rm
intel_telemetry.h	4060	0644	edit dl rm
invpcid.h	1604	0644	edit dl rm
io.h	11872	0644	edit dl rm
iomap.h	1228	0644	edit dl rm
iommu.h	935	0644	edit dl rm
iosf_mbi.h	7354	0644	edit dl rm
io_apic.h	5890	0644	edit dl rm
ipi.h	2873	0644	edit dl rm
irq.h	1415	0644	edit dl rm
irqdomain.h	1796	0644	edit dl rm
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kasan.h	1291	0644	edit dl rm
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kbdleds.h	454	0644	edit dl rm
Kbuild	319	0644	edit dl rm
kdebug.h	1042	0644	edit dl rm
kexec-bzimage64.h	195	0644	edit dl rm
kexec.h	5843	0644	edit dl rm
kgdb.h	2143	0644	edit dl rm
kprobes.h	3701	0644	edit dl rm
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kvmclock.h	506	0644	edit dl rm
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kvm_types.h	178	0644	edit dl rm
kvm_vcpu_regs.h	606	0644	edit dl rm
linkage.h	1268	0644	edit dl rm
livepatch.h	1039	0644	edit dl rm
local.h	3925	0644	edit dl rm
local64.h	33	0644	edit dl rm
mach_timer.h	1590	0644	edit dl rm
mach_traps.h	1013	0644	edit dl rm
math_emu.h	395	0644	edit dl rm
mc146818rtc.h	2835	0644	edit dl rm
mce.h	11909	0644	edit dl rm
mcsafe_test.h	1418	0644	edit dl rm
memtype.h	815	0644	edit dl rm
mem_encrypt.h	3543	0644	edit dl rm
microcode.h	3557	0644	edit dl rm
microcode_amd.h	1373	0644	edit dl rm
microcode_intel.h	2619	0644	edit dl rm
misc.h	143	0644	edit dl rm
mmconfig.h	374	0644	edit dl rm
mmu.h	1689	0644	edit dl rm
mmu_context.h	10118	0644	edit dl rm
mmx.h	337	0644	edit dl rm
mmzone.h	129	0644	edit dl rm
mmzone_32.h	1188	0644	edit dl rm
mmzone_64.h	430	0644	edit dl rm
module.h	2096	0644	edit dl rm
mpspec.h	4023	0644	edit dl rm
mpspec_def.h	4256	0644	edit dl rm
mpx.h	3125	0644	edit dl rm
mshyperv.h	10142	0644	edit dl rm
msi.h	1508	0644	edit dl rm
msidef.h	1814	0644	edit dl rm
msr-index.h	42400	0644	edit dl rm
msr-trace.h	1387	0644	edit dl rm
msr.h	11290	0644	edit dl rm
mtrr.h	4753	0644	edit dl rm
mwait.h	4968	0644	edit dl rm
nmi.h	1496	0644	edit dl rm
nops.h	4412	0644	edit dl rm
nospec-branch.h	14205	0644	edit dl rm
numa.h	2228	0644	edit dl rm
numa_32.h	256	0644	edit dl rm
olpc.h	3240	0644	edit dl rm
olpc_ofw.h	1128	0644	edit dl rm
orc_lookup.h	1665	0644	edit dl rm
orc_types.h	3577	0644	edit dl rm
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paravirt.h	24608	0644	edit dl rm
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parport.h	314	0644	edit dl rm
pci-direct.h	740	0644	edit dl rm
pci-functions.h	654	0644	edit dl rm
pci.h	3288	0644	edit dl rm
pci_64.h	684	0644	edit dl rm
pci_x86.h	6283	0644	edit dl rm
percpu.h	20267	0644	edit dl rm
perf_event.h	17896	0644	edit dl rm
perf_event_p4.h	26731	0644	edit dl rm
pgalloc.h	6591	0644	edit dl rm
pgtable-2level.h	2815	0644	edit dl rm
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pgtable-3level.h	8832	0644	edit dl rm
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pgtable-invert.h	1091	0644	edit dl rm
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pgtable_types.h	17149	0644	edit dl rm
pkeys.h	3542	0644	edit dl rm
pkru.h	1346	0644	edit dl rm
platform_sst_audio.h	3290	0644	edit dl rm
pm-trace.h	611	0644	edit dl rm
posix_types.h	144	0644	edit dl rm
preempt.h	3217	0644	edit dl rm
probe_roms.h	273	0644	edit dl rm
processor-cyrix.h	879	0644	edit dl rm
processor-flags.h	1750	0644	edit dl rm
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prom.h	1028	0644	edit dl rm
proto.h	1313	0644	edit dl rm
pti.h	429	0644	edit dl rm
ptrace.h	8996	0644	edit dl rm
purgatory.h	235	0644	edit dl rm
pvclock-abi.h	1530	0644	edit dl rm
pvclock.h	2702	0644	edit dl rm
qrwlock.h	199	0644	edit dl rm
qspinlock.h	2598	0644	edit dl rm
qspinlock_paravirt.h	1908	0644	edit dl rm
realmode.h	2064	0644	edit dl rm
reboot.h	898	0644	edit dl rm
reboot_fixups.h	183	0644	edit dl rm
refcount.h	2911	0644	edit dl rm
required-features.h	3043	0644	edit dl rm
resctrl.h	3064	0644	edit dl rm
rio.h	2630	0644	edit dl rm
rmwcc.h	2259	0644	edit dl rm
seccomp.h	510	0644	edit dl rm
sections.h	916	0644	edit dl rm
segment.h	11184	0644	edit dl rm
serial.h	1137	0644	edit dl rm
setup.h	3751	0644	edit dl rm
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set_memory.h	5381	0644	edit dl rm
sev-common.h	4867	0644	edit dl rm
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sgx.h	13157	0644	edit dl rm
shmparam.h	193	0644	edit dl rm
sigcontext.h	261	0644	edit dl rm
sigframe.h	2339	0644	edit dl rm
sighandling.h	730	0644	edit dl rm
signal.h	2424	0644	edit dl rm
simd.h	287	0644	edit dl rm
smap.h	2247	0644	edit dl rm
smp.h	5500	0644	edit dl rm
sparsemem.h	994	0644	edit dl rm
spec-ctrl.h	3143	0644	edit dl rm
special_insns.h	7536	0644	edit dl rm
spinlock.h	1214	0644	edit dl rm
spinlock_types.h	719	0644	edit dl rm
sta2x11.h	352	0644	edit dl rm
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Edit: /usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/arch/x86/include/asm/apic.h (14661B)

/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _ASM_X86_APIC_H
#define _ASM_X86_APIC_H

#include <linux/cpumask.h>

#include <asm/alternative.h>
#include <asm/cpufeature.h>
#include <asm/apicdef.h>
#include <linux/atomic.h>
#include <asm/fixmap.h>
#include <asm/mpspec.h>
#include <asm/msr.h>
#include <asm/hardirq.h>

#define ARCH_APICTIMER_STOPS_ON_C3	1

/*
 * Debugging macros
 */
#define APIC_QUIET   0
#define APIC_VERBOSE 1
#define APIC_DEBUG   2

/* Macros for apic_extnmi which controls external NMI masking */
#define APIC_EXTNMI_BSP		0 /* Default */
#define APIC_EXTNMI_ALL		1
#define APIC_EXTNMI_NONE	2

/*
 * Define the default level of output to be very little
 * This can be turned up by using apic=verbose for more
 * information and apic=debug for _lots_ of information.
 * apic_verbosity is defined in apic.c
 */
#define apic_printk(v, s, a...) do {       \
		if ((v) <= apic_verbosity) \
			printk(s, ##a);    \
	} while (0)

#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
extern void generic_apic_probe(void);
#else
static inline void generic_apic_probe(void)
{
}
#endif

#ifdef CONFIG_X86_LOCAL_APIC

extern unsigned int apic_verbosity;
extern int local_apic_timer_c2_ok;

extern int disable_apic;
extern unsigned int lapic_timer_period;

extern enum apic_intr_mode_id apic_intr_mode;
enum apic_intr_mode_id {
	APIC_PIC,
	APIC_VIRTUAL_WIRE,
	APIC_VIRTUAL_WIRE_NO_CONFIG,
	APIC_SYMMETRIC_IO,
	APIC_SYMMETRIC_IO_NO_ROUTING
};

#ifdef CONFIG_SMP
extern void __inquire_remote_apic(int apicid);
#else /* CONFIG_SMP */
static inline void __inquire_remote_apic(int apicid)
{
}
#endif /* CONFIG_SMP */

static inline void default_inquire_remote_apic(int apicid)
{
	if (apic_verbosity >= APIC_DEBUG)
		__inquire_remote_apic(apicid);
}

/*
 * With 82489DX we can't rely on apic feature bit
 * retrieved via cpuid but still have to deal with
 * such an apic chip so we assume that SMP configuration
 * is found from MP table (64bit case uses ACPI mostly
 * which set smp presence flag as well so we are safe
 * to use this helper too).
 */
static inline bool apic_from_smp_config(void)
{
	return smp_found_config && !disable_apic;
}

/*
 * Basic functions accessing APICs.
 */
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#endif

extern int setup_profiling_timer(unsigned int);

static inline void native_apic_mem_write(u32 reg, u32 v)
{
	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);

alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),
		       ASM_OUTPUT2("0" (v), "m" (*addr)));
}

static inline u32 native_apic_mem_read(u32 reg)
{
	return *((volatile u32 *)(APIC_BASE + reg));
}

extern void native_apic_wait_icr_idle(void);
extern u32 native_safe_apic_wait_icr_idle(void);
extern void native_apic_icr_write(u32 low, u32 id);
extern u64 native_apic_icr_read(void);

static inline bool apic_is_x2apic_enabled(void)
{
	u64 msr;

if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
		return false;
	return msr & X2APIC_ENABLE;
}

extern void enable_IR_x2apic(void);

extern int get_physical_broadcast(void);

extern int lapic_get_maxlvt(void);
extern void clear_local_APIC(void);
extern void disconnect_bsp_APIC(int virt_wire_setup);
extern void disable_local_APIC(void);
extern void lapic_shutdown(void);
extern void sync_Arb_IDs(void);
extern void init_bsp_APIC(void);
extern void apic_intr_mode_select(void);
extern void apic_intr_mode_init(void);
extern void init_apic_mappings(void);
void register_lapic_address(unsigned long address);
extern void setup_boot_APIC_clock(void);
extern void setup_secondary_APIC_clock(void);
extern void lapic_update_tsc_freq(void);

#ifdef CONFIG_X86_64
static inline int apic_force_enable(unsigned long addr)
{
	return -1;
}
#else
extern int apic_force_enable(unsigned long addr);
#endif

extern void apic_bsp_setup(bool upmode);
extern void apic_ap_setup(void);

/*
 * On 32bit this is mach-xxx local
 */
#ifdef CONFIG_X86_64
extern int apic_is_clustered_box(void);
#else
static inline int apic_is_clustered_box(void)
{
	return 0;
}
#endif

extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
extern void lapic_assign_system_vectors(void);
extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
extern void lapic_online(void);
extern void lapic_offline(void);
extern bool apic_needs_pit(void);

#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }
#define local_apic_timer_c2_ok		1
static inline void init_apic_mappings(void) { }
static inline void disable_local_APIC(void) { }
# define setup_boot_APIC_clock x86_init_noop
# define setup_secondary_APIC_clock x86_init_noop
static inline void lapic_update_tsc_freq(void) { }
static inline void init_bsp_APIC(void) { }
static inline void apic_intr_mode_select(void) { }
static inline void apic_intr_mode_init(void) { }
static inline void lapic_assign_system_vectors(void) { }
static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
static inline bool apic_needs_pit(void) { return true; }
#endif /* !CONFIG_X86_LOCAL_APIC */

#ifdef CONFIG_X86_X2APIC
/*
 * Make previous memory operations globally visible before
 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
 * mfence for this.
 */
static inline void x2apic_wrmsr_fence(void)
{
	asm volatile("mfence" : : : "memory");
}

static inline void native_apic_msr_write(u32 reg, u32 v)
{
	if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
	    reg == APIC_LVR)
		return;

wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
}

static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
{
	__wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
}

static inline u32 native_apic_msr_read(u32 reg)
{
	u64 msr;

if (reg == APIC_DFR)
		return -1;

rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
	return (u32)msr;
}

static inline void native_x2apic_wait_icr_idle(void)
{
	/* no need to wait for icr idle in x2apic */
	return;
}

static inline u32 native_safe_x2apic_wait_icr_idle(void)
{
	/* no need to wait for icr idle in x2apic */
	return 0;
}

static inline void native_x2apic_icr_write(u32 low, u32 id)
{
	wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
}

static inline u64 native_x2apic_icr_read(void)
{
	unsigned long val;

rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
	return val;
}

extern int x2apic_mode;
extern int x2apic_phys;
extern void __init x2apic_set_max_apicid(u32 apicid);
extern void __init check_x2apic(void);
extern void x2apic_setup(void);
static inline int x2apic_enabled(void)
{
	return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
}

#define x2apic_supported()	(boot_cpu_has(X86_FEATURE_X2APIC))
#else /* !CONFIG_X86_X2APIC */
static inline void check_x2apic(void) { }
static inline void x2apic_setup(void) { }
static inline int x2apic_enabled(void) { return 0; }

#define x2apic_mode		(0)
#define	x2apic_supported()	(0)
#endif /* !CONFIG_X86_X2APIC */

struct irq_data;

/*
 * Copyright 2004 James Cleverdon, IBM.
 *
 * Generic APIC sub-arch data struct.
 *
 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 * James Cleverdon.
 */
struct apic {
	/* Hotpath functions first */
	void	(*eoi_write)(u32 reg, u32 v);
	void	(*native_eoi_write)(u32 reg, u32 v);
	void	(*write)(u32 reg, u32 v);
	u32	(*read)(u32 reg);

/* IPI related functions */
	void	(*wait_icr_idle)(void);
	u32	(*safe_wait_icr_idle)(void);

void	(*send_IPI)(int cpu, int vector);
	void	(*send_IPI_mask)(const struct cpumask *mask, int vector);
	void	(*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
	void	(*send_IPI_allbutself)(int vector);
	void	(*send_IPI_all)(int vector);
	void	(*send_IPI_self)(int vector);

/* dest_logical is used by the IPI functions */
	u32	dest_logical;
	u32	disable_esr;

RH_KABI_REPLACE(u32 irq_delivery_mode, enum apic_delivery_modes delivery_mode)
	u32	irq_dest_mode;

u32	(*calc_dest_apicid)(unsigned int cpu);

/* ICR related functions */
	u64	(*icr_read)(void);
	void	(*icr_write)(u32 low, u32 high);

/* Probe, setup and smpboot functions */
	int	(*probe)(void);
	int	(*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
	int	(*apic_id_valid)(u32 apicid);
	int	(*apic_id_registered)(void);

bool	(*check_apicid_used)(physid_mask_t *map, int apicid);
	void	(*init_apic_ldr)(void);
	void	(*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
	void	(*setup_apic_routing)(void);
	int	(*cpu_present_to_apicid)(int mps_cpu);
	void	(*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
	int	(*check_phys_apicid_present)(int phys_apicid);
	int	(*phys_pkg_id)(int cpuid_apic, int index_msb);

u32	(*get_apic_id)(unsigned long x);
	u32	(*set_apic_id)(unsigned int id);

/* wakeup_secondary_cpu */
	int	(*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);

void	(*inquire_remote_apic)(int apicid);

#ifdef CONFIG_X86_32
	/*
	 * Called very early during boot from get_smp_config().  It should
	 * return the logical apicid.  x86_[bios]_cpu_to_apicid is
	 * initialized before this function is called.
	 *
	 * If logical apicid can't be determined that early, the function
	 * may return BAD_APICID.  Logical apicid will be configured after
	 * init_apic_ldr() while bringing up CPUs.  Note that NUMA affinity
	 * won't be applied properly during early boot in this case.
	 */
	int (*x86_32_early_logical_apicid)(int cpu);
#endif
	char	*name;

/* wakeup secondary CPU using 64-bit wakeup point */
	RH_KABI_EXTEND(int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip))
};

/*
 * Pointer to the local APIC driver in use on this system (there's
 * always just one such driver in use - the kernel decides via an
 * early probing process which one it picks - and then sticks to it):
 */
extern struct apic *apic;

/*
 * APIC drivers are probed based on how they are listed in the .apicdrivers
 * section. So the order is important and enforced by the ordering
 * of different apic driver files in the Makefile.
 *
 * For the files having two apic drivers, we use apic_drivers()
 * to enforce the order with in them.
 */
#define apic_driver(sym)					\
	static const struct apic *__apicdrivers_##sym __used		\
	__aligned(sizeof(struct apic *))			\
	__section(.apicdrivers) = { &sym }

#define apic_drivers(sym1, sym2)					\
	static struct apic *__apicdrivers_##sym1##sym2[2] __used	\
	__aligned(sizeof(struct apic *))				\
	__section(.apicdrivers) = { &sym1, &sym2 }

extern struct apic *__apicdrivers[], *__apicdrivers_end[];

/*
 * APIC functionality to boot other CPUs - only used on SMP:
 */
#ifdef CONFIG_SMP
extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
extern int lapic_can_unplug_cpu(void);
#endif

#ifdef CONFIG_X86_LOCAL_APIC

static inline u32 apic_read(u32 reg)
{
	return apic->read(reg);
}

static inline void apic_write(u32 reg, u32 val)
{
	apic->write(reg, val);
}

static inline void apic_eoi(void)
{
	apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
}

static inline u64 apic_icr_read(void)
{
	return apic->icr_read();
}

static inline void apic_icr_write(u32 low, u32 high)
{
	apic->icr_write(low, high);
}

static inline void apic_wait_icr_idle(void)
{
	apic->wait_icr_idle();
}

static inline u32 safe_apic_wait_icr_idle(void)
{
	return apic->safe_wait_icr_idle();
}

extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));

#else /* CONFIG_X86_LOCAL_APIC */

static inline u32 apic_read(u32 reg) { return 0; }
static inline void apic_write(u32 reg, u32 val) { }
static inline void apic_eoi(void) { }
static inline u64 apic_icr_read(void) { return 0; }
static inline void apic_icr_write(u32 low, u32 high) { }
static inline void apic_wait_icr_idle(void) { }
static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}

#endif /* CONFIG_X86_LOCAL_APIC */

extern void apic_ack_irq(struct irq_data *data);

static inline void ack_APIC_irq(void)
{
	/*
	 * ack_APIC_irq() actually gets compiled as a single instruction
	 * ... yummie.
	 */
	apic_eoi();
}

static inline bool lapic_vector_set_in_irr(unsigned int vector)
{
	u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));

return !!(irr & (1U << (vector % 32)));
}

static inline unsigned default_get_apic_id(unsigned long x)
{
	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));

if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
		return (x >> 24) & 0xFF;
	else
		return (x >> 24) & 0x0F;
}

/*
 * Warm reset vector position:
 */
#define TRAMPOLINE_PHYS_LOW		0x467
#define TRAMPOLINE_PHYS_HIGH		0x469

#ifdef CONFIG_X86_64
extern void apic_send_IPI_self(int vector);
#endif

extern void generic_bigsmp_probe(void);

#ifdef CONFIG_X86_LOCAL_APIC

#include <asm/smp.h>

#define APIC_DFR_VALUE	(APIC_DFR_FLAT)

DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);

extern struct apic apic_noop;

static inline unsigned int read_apic_id(void)
{
	unsigned int reg = apic_read(APIC_ID);

return apic->get_apic_id(reg);
}

#ifdef CONFIG_X86_64
typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler);
#endif

extern int default_apic_id_valid(u32 apicid);
extern int default_acpi_madt_oem_check(char *, char *);
extern void default_setup_apic_routing(void);

extern u32 apic_default_calc_apicid(unsigned int cpu);
extern u32 apic_flat_calc_apicid(unsigned int cpu);

extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
extern int default_cpu_present_to_apicid(int mps_cpu);
extern int default_check_phys_apicid_present(int phys_apicid);

#endif /* CONFIG_X86_LOCAL_APIC */

#ifdef CONFIG_SMP
bool apic_id_is_primary_thread(unsigned int id);
#else
static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
#endif

extern void irq_enter(void);
extern void irq_exit(void);

static inline void entering_irq(void)
{
	irq_enter();
	kvm_set_cpu_l1tf_flush_l1d();
}

static inline void entering_ack_irq(void)
{
	entering_irq();
	ack_APIC_irq();
}

static inline void ipi_entering_ack_irq(void)
{
	irq_enter();
	ack_APIC_irq();
	kvm_set_cpu_l1tf_flush_l1d();
}

static inline void exiting_irq(void)
{
	irq_exit();
}

static inline void exiting_ack_irq(void)
{
	ack_APIC_irq();
	irq_exit();
}

struct msi_msg;
struct irq_cfg;

extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
				  bool dmar);

extern void ioapic_zap_locks(void);

#endif /* _ASM_X86_APIC_H */

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