FM / asm

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/arch/x86/include/asm/

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/arch/x86/include/asm

Name	Size	Mode	Actions
crypto/	-	0755	rm
e820/	-	0755	rm
fpu/	-	0755	rm
numachip/	-	0755	rm
shared/	-	0755	rm
trace/	-	0755	rm
uv/	-	0755	rm
vdso/	-	0755	rm
xen/	-	0755	rm
a.out-core.h	1931	0644	edit dl rm
acenv.h	1596	0644	edit dl rm
acpi.h	5300	0644	edit dl rm
agp.h	1070	0644	edit dl rm
alternative.h	11407	0644	edit dl rm
amd-ibs.h	5020	0644	edit dl rm
amd_hsmp.h	364	0644	edit dl rm
amd_nb.h	3086	0644	edit dl rm
apb_timer.h	1466	0644	edit dl rm
apic.h	14661	0644	edit dl rm
apicdef.h	11565	0644	edit dl rm
apic_flat_64.h	151	0644	edit dl rm
apm.h	1768	0644	edit dl rm
archrandom.h	3221	0644	edit dl rm
arch_hweight.h	1311	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	946	0644	edit dl rm
asm.h	5186	0644	edit dl rm
atomic.h	6279	0644	edit dl rm
atomic64_32.h	8150	0644	edit dl rm
atomic64_64.h	5933	0644	edit dl rm
audit.h	170	0644	edit dl rm
barrier.h	2471	0644	edit dl rm
bios_ebda.h	914	0644	edit dl rm
bitops.h	10727	0644	edit dl rm
boot.h	1825	0644	edit dl rm
bootparam_utils.h	2907	0644	edit dl rm
bug.h	2117	0644	edit dl rm
bugs.h	533	0644	edit dl rm
cache.h	641	0644	edit dl rm
cacheflush.h	306	0644	edit dl rm
cacheinfo.h	209	0644	edit dl rm
calgary.h	2370	0644	edit dl rm
ce4100.h	121	0644	edit dl rm
checksum.h	133	0644	edit dl rm
checksum_32.h	4964	0644	edit dl rm
checksum_64.h	5541	0644	edit dl rm
clocksource.h	480	0644	edit dl rm
cmdline.h	302	0644	edit dl rm
cmpxchg.h	7891	0644	edit dl rm
cmpxchg_32.h	3247	0644	edit dl rm
cmpxchg_64.h	552	0644	edit dl rm
coco.h	482	0644	edit dl rm
compat.h	4861	0644	edit dl rm
cpu.h	2607	0644	edit dl rm
cpufeature.h	9470	0644	edit dl rm
cpufeatures.h	32845	0644	edit dl rm
cpuid.h	498	0644	edit dl rm
cpuidle_haltpoll.h	189	0644	edit dl rm
cpumask.h	408	0644	edit dl rm
cpu_device_id.h	8109	0644	edit dl rm
cpu_entry_area.h	4162	0644	edit dl rm
crash.h	300	0644	edit dl rm
current.h	443	0644	edit dl rm
debugreg.h	3411	0644	edit dl rm
delay.h	275	0644	edit dl rm
desc.h	12274	0644	edit dl rm
desc_defs.h	3396	0644	edit dl rm
device.h	328	0644	edit dl rm
disabled-features.h	3559	0644	edit dl rm
div64.h	2189	0644	edit dl rm
dma-mapping.h	288	0644	edit dl rm
dma.h	9827	0644	edit dl rm
dmi.h	556	0644	edit dl rm
dwarf2.h	2487	0644	edit dl rm
edac.h	474	0644	edit dl rm
efi.h	7416	0644	edit dl rm
elf.h	12640	0644	edit dl rm
emergency-restart.h	202	0644	edit dl rm
emulate_prefix.h	484	0644	edit dl rm
enclu.h	181	0644	edit dl rm
entry_arch.h	1922	0644	edit dl rm
espfix.h	426	0644	edit dl rm
exec.h	37	0644	edit dl rm
export.h	120	0644	edit dl rm
extable.h	1300	0644	edit dl rm
fb.h	540	0644	edit dl rm
fixmap.h	6381	0644	edit dl rm
floppy.h	6748	0644	edit dl rm
frame.h	2237	0644	edit dl rm
fsgsbase.h	2072	0644	edit dl rm
ftrace.h	2777	0644	edit dl rm
futex.h	2269	0644	edit dl rm
gart.h	2682	0644	edit dl rm
genapic.h	22	0644	edit dl rm
geode.h	842	0644	edit dl rm
hardirq.h	2207	0644	edit dl rm
highmem.h	2466	0644	edit dl rm
hpet.h	3461	0644	edit dl rm
hugetlb.h	1867	0644	edit dl rm
hw_breakpoint.h	2112	0644	edit dl rm
hw_irq.h	4126	0644	edit dl rm
hyperv-tlfs.h	22337	0644	edit dl rm
hypervisor.h	1975	0644	edit dl rm
i8259.h	1975	0644	edit dl rm
ia32.h	1789	0644	edit dl rm
ia32_unistd.h	313	0644	edit dl rm
imr.h	1849	0644	edit dl rm
inat.h	6736	0644	edit dl rm
inat_types.h	1013	0644	edit dl rm
init.h	632	0644	edit dl rm
insn-eval.h	1546	0644	edit dl rm
insn.h	8098	0644	edit dl rm
inst.h	5453	0644	edit dl rm
intel-family.h	5168	0644	edit dl rm
intel-mid.h	5025	0644	edit dl rm
intel_ds.h	849	0644	edit dl rm
intel_mid_vrtc.h	330	0644	edit dl rm
intel_pconfig.h	1545	0644	edit dl rm
intel_pmc_ipc.h	2267	0644	edit dl rm
intel_pt.h	1276	0644	edit dl rm
intel_punit_ipc.h	4666	0644	edit dl rm
intel_scu_ipc.h	2351	0644	edit dl rm
intel_telemetry.h	4060	0644	edit dl rm
invpcid.h	1604	0644	edit dl rm
io.h	11872	0644	edit dl rm
iomap.h	1228	0644	edit dl rm
iommu.h	935	0644	edit dl rm
iosf_mbi.h	7354	0644	edit dl rm
io_apic.h	5890	0644	edit dl rm
ipi.h	2873	0644	edit dl rm
irq.h	1415	0644	edit dl rm
irqdomain.h	1796	0644	edit dl rm
irqflags.h	4161	0644	edit dl rm
irq_regs.h	683	0644	edit dl rm
irq_remapping.h	2865	0644	edit dl rm
irq_vectors.h	4105	0644	edit dl rm
irq_work.h	465	0644	edit dl rm
ist.h	735	0644	edit dl rm
jailhouse_para.h	449	0644	edit dl rm
jump_label.h	2529	0644	edit dl rm
kasan.h	1291	0644	edit dl rm
kaslr.h	314	0644	edit dl rm
kbdleds.h	454	0644	edit dl rm
Kbuild	319	0644	edit dl rm
kdebug.h	1042	0644	edit dl rm
kexec-bzimage64.h	195	0644	edit dl rm
kexec.h	5843	0644	edit dl rm
kgdb.h	2143	0644	edit dl rm
kprobes.h	3701	0644	edit dl rm
kvm-x86-ops.h	3989	0644	edit dl rm
kvmclock.h	506	0644	edit dl rm
kvm_host.h	63925	0644	edit dl rm
kvm_page_track.h	2700	0644	edit dl rm
kvm_para.h	4422	0644	edit dl rm
kvm_types.h	178	0644	edit dl rm
kvm_vcpu_regs.h	606	0644	edit dl rm
linkage.h	1268	0644	edit dl rm
livepatch.h	1039	0644	edit dl rm
local.h	3925	0644	edit dl rm
local64.h	33	0644	edit dl rm
mach_timer.h	1590	0644	edit dl rm
mach_traps.h	1013	0644	edit dl rm
math_emu.h	395	0644	edit dl rm
mc146818rtc.h	2835	0644	edit dl rm
mce.h	11909	0644	edit dl rm
mcsafe_test.h	1418	0644	edit dl rm
memtype.h	815	0644	edit dl rm
mem_encrypt.h	3543	0644	edit dl rm
microcode.h	3557	0644	edit dl rm
microcode_amd.h	1373	0644	edit dl rm
microcode_intel.h	2619	0644	edit dl rm
misc.h	143	0644	edit dl rm
mmconfig.h	374	0644	edit dl rm
mmu.h	1689	0644	edit dl rm
mmu_context.h	10118	0644	edit dl rm
mmx.h	337	0644	edit dl rm
mmzone.h	129	0644	edit dl rm
mmzone_32.h	1188	0644	edit dl rm
mmzone_64.h	430	0644	edit dl rm
module.h	2096	0644	edit dl rm
mpspec.h	4023	0644	edit dl rm
mpspec_def.h	4256	0644	edit dl rm
mpx.h	3125	0644	edit dl rm
mshyperv.h	10142	0644	edit dl rm
msi.h	1508	0644	edit dl rm
msidef.h	1814	0644	edit dl rm
msr-index.h	42400	0644	edit dl rm
msr-trace.h	1387	0644	edit dl rm
msr.h	11290	0644	edit dl rm
mtrr.h	4753	0644	edit dl rm
mwait.h	4968	0644	edit dl rm
nmi.h	1496	0644	edit dl rm
nops.h	4412	0644	edit dl rm
nospec-branch.h	14205	0644	edit dl rm
numa.h	2228	0644	edit dl rm
numa_32.h	256	0644	edit dl rm
olpc.h	3240	0644	edit dl rm
olpc_ofw.h	1128	0644	edit dl rm
orc_lookup.h	1665	0644	edit dl rm
orc_types.h	3577	0644	edit dl rm
page.h	2517	0644	edit dl rm
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paravirt.h	24608	0644	edit dl rm
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parport.h	314	0644	edit dl rm
pci-direct.h	740	0644	edit dl rm
pci-functions.h	654	0644	edit dl rm
pci.h	3288	0644	edit dl rm
pci_64.h	684	0644	edit dl rm
pci_x86.h	6283	0644	edit dl rm
percpu.h	20267	0644	edit dl rm
perf_event.h	17896	0644	edit dl rm
perf_event_p4.h	26731	0644	edit dl rm
pgalloc.h	6591	0644	edit dl rm
pgtable-2level.h	2815	0644	edit dl rm
pgtable-2level_types.h	867	0644	edit dl rm
pgtable-3level.h	8832	0644	edit dl rm
pgtable-3level_types.h	1007	0644	edit dl rm
pgtable-invert.h	1091	0644	edit dl rm
pgtable.h	35801	0644	edit dl rm
pgtable_32.h	3159	0644	edit dl rm
pgtable_32_types.h	2121	0644	edit dl rm
pgtable_64.h	7474	0644	edit dl rm
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pgtable_types.h	17149	0644	edit dl rm
pkeys.h	3542	0644	edit dl rm
pkru.h	1346	0644	edit dl rm
platform_sst_audio.h	3290	0644	edit dl rm
pm-trace.h	611	0644	edit dl rm
posix_types.h	144	0644	edit dl rm
preempt.h	3217	0644	edit dl rm
probe_roms.h	273	0644	edit dl rm
processor-cyrix.h	879	0644	edit dl rm
processor-flags.h	1750	0644	edit dl rm
processor.h	24480	0644	edit dl rm
prom.h	1028	0644	edit dl rm
proto.h	1313	0644	edit dl rm
pti.h	429	0644	edit dl rm
ptrace.h	8996	0644	edit dl rm
purgatory.h	235	0644	edit dl rm
pvclock-abi.h	1530	0644	edit dl rm
pvclock.h	2702	0644	edit dl rm
qrwlock.h	199	0644	edit dl rm
qspinlock.h	2598	0644	edit dl rm
qspinlock_paravirt.h	1908	0644	edit dl rm
realmode.h	2064	0644	edit dl rm
reboot.h	898	0644	edit dl rm
reboot_fixups.h	183	0644	edit dl rm
refcount.h	2911	0644	edit dl rm
required-features.h	3043	0644	edit dl rm
resctrl.h	3064	0644	edit dl rm
rio.h	2630	0644	edit dl rm
rmwcc.h	2259	0644	edit dl rm
seccomp.h	510	0644	edit dl rm
sections.h	916	0644	edit dl rm
segment.h	11184	0644	edit dl rm
serial.h	1137	0644	edit dl rm
setup.h	3751	0644	edit dl rm
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set_memory.h	5381	0644	edit dl rm
sev-common.h	4867	0644	edit dl rm
sev.h	6965	0644	edit dl rm
sgx.h	13157	0644	edit dl rm
shmparam.h	193	0644	edit dl rm
sigcontext.h	261	0644	edit dl rm
sigframe.h	2339	0644	edit dl rm
sighandling.h	730	0644	edit dl rm
signal.h	2424	0644	edit dl rm
simd.h	287	0644	edit dl rm
smap.h	2247	0644	edit dl rm
smp.h	5500	0644	edit dl rm
sparsemem.h	994	0644	edit dl rm
spec-ctrl.h	3143	0644	edit dl rm
special_insns.h	7536	0644	edit dl rm
spinlock.h	1214	0644	edit dl rm
spinlock_types.h	719	0644	edit dl rm
sta2x11.h	352	0644	edit dl rm
stackprotector.h	3966	0644	edit dl rm
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string.h	129	0644	edit dl rm
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string_64.h	4237	0644	edit dl rm
suspend.h	503	0644	edit dl rm
suspend_32.h	938	0644	edit dl rm
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svm.h	14672	0644	edit dl rm
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sync_bitops.h	3503	0644	edit dl rm
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text-patching.h	4812	0644	edit dl rm
thermal.h	428	0644	edit dl rm
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time.h	331	0644	edit dl rm
timer.h	1027	0644	edit dl rm
timex.h	305	0644	edit dl rm
tlb.h	1103	0644	edit dl rm
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topology.h	6654	0644	edit dl rm
trace_clock.h	406	0644	edit dl rm
trapnr.h	1316	0644	edit dl rm
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uaccess.h	21233	0644	edit dl rm
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unaligned.h	345	0644	edit dl rm
unistd.h	1482	0644	edit dl rm
unwind.h	3220	0644	edit dl rm
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user.h	2257	0644	edit dl rm
user32.h	2156	0644	edit dl rm
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user_64.h	5339	0644	edit dl rm
vdso.h	1400	0644	edit dl rm
vga.h	740	0644	edit dl rm
vgtod.h	518	0644	edit dl rm
virtext.h	3102	0644	edit dl rm
vm86.h	2212	0644	edit dl rm
vmware.h	1942	0644	edit dl rm
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vmxfeatures.h	6049	0644	edit dl rm
vsyscall.h	920	0644	edit dl rm
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Edit: /usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/arch/x86/include/asm/processor.h (24480B)

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_PROCESSOR_H
#define _ASM_X86_PROCESSOR_H

#include <asm/processor-flags.h>

/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
struct vm86;

#include <asm/math_emu.h>
#include <asm/segment.h>
#include <asm/types.h>
#include <uapi/asm/sigcontext.h>
#include <asm/current.h>
#include <asm/cpufeatures.h>
#include <asm/page.h>
#include <asm/pgtable_types.h>
#include <asm/percpu.h>
#include <asm/msr.h>
#include <asm/desc_defs.h>
#include <asm/nops.h>
#include <asm/special_insns.h>
#include <asm/fpu/types.h>
#include <asm/unwind_hints.h>
#include <asm/vmxfeatures.h>
#include <asm/vdso/processor.h>

#include <linux/personality.h>
#include <linux/cache.h>
#include <linux/threads.h>
#include <linux/math64.h>
#include <linux/err.h>
#include <linux/irqflags.h>
#include <linux/mem_encrypt.h>
#include <linux/rh_kabi.h>

/*
 * We handle most unaligned accesses in hardware.  On the other hand
 * unaligned DMA can be quite expensive on some Nehalem processors.
 *
 * Based on this we disable the IP header alignment in network drivers.
 */
#define NET_IP_ALIGN	0

#define HBP_NUM 4
/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
static inline void *current_text_addr(void)
{
	void *pc;

asm volatile("mov $1f, %0; 1:":"=r" (pc));

return pc;
}

/*
 * These alignment constraints are for performance in the vSMP case,
 * but in the task_struct case we must also meet hardware imposed
 * alignment requirements of the FPU state:
 */
#ifdef CONFIG_X86_VSMP
# define ARCH_MIN_TASKALIGN		(1 << INTERNODE_CACHE_SHIFT)
# define ARCH_MIN_MMSTRUCT_ALIGN	(1 << INTERNODE_CACHE_SHIFT)
#else
# define ARCH_MIN_TASKALIGN		__alignof__(union fpregs_state)
# define ARCH_MIN_MMSTRUCT_ALIGN	0
#endif

enum tlb_infos {
	ENTRIES,
	NR_INFO
};

extern u16 __read_mostly tlb_lli_4k[NR_INFO];
extern u16 __read_mostly tlb_lli_2m[NR_INFO];
extern u16 __read_mostly tlb_lli_4m[NR_INFO];
extern u16 __read_mostly tlb_lld_4k[NR_INFO];
extern u16 __read_mostly tlb_lld_2m[NR_INFO];
extern u16 __read_mostly tlb_lld_4m[NR_INFO];
extern u16 __read_mostly tlb_lld_1g[NR_INFO];

struct cpuinfo_x86_extended_rh {
	u16			cpu_die_id;
	u16			logical_die_id;
	int                     x86_cache_mbm_width_offset;
	/*  Is SMT active on this core? */
	bool			smt_active;
#ifdef CONFIG_X86_VMX_FEATURE_NAMES
	__u32			vmx_capability[NVMXINTS];
#endif
};

/*
 *  CPU type and hardware bug flags. Kept separately for each CPU.
 *  Members of this structure are referenced in head_32.S, so think twice
 *  before touching them. [mj]
 */

struct cpuinfo_x86 {
	__u8			x86;		/* CPU family */
	__u8			x86_vendor;	/* CPU vendor */
	__u8			x86_model;
	__u8			x86_stepping;
#ifdef CONFIG_X86_64
	/* Number of 4K pages in DTLB/ITLB combined(in pages): */
	int			x86_tlbsize;
#endif
	__u8			x86_virt_bits;
	__u8			x86_phys_bits;
	/* CPUID returned core id bits: */
	__u8			x86_coreid_bits;
	__u8			cu_id;
	/* Max extended CPUID function supported: */
	__u32			extended_cpuid_level;
	/* Maximum supported CPUID level, -1=no CPUID: */
	int			cpuid_level;
	__u32			x86_capability[NCAPINTS + NBUGINTS];
	char			x86_vendor_id[16];
	char			x86_model_id[64];
	/* in KB - valid for CPUS which support this call: */
	unsigned int		x86_cache_size;
	int			x86_cache_alignment;	/* In bytes */
	/* Cache QoS architectural values, valid only on the BSP: */
	int			x86_cache_max_rmid;	/* max index */
	int			x86_cache_occ_scale;	/* scale to bytes */
	int			x86_power;
	unsigned long		loops_per_jiffy;
	/* cpuid returned max cores value: */
	u16			x86_max_cores;
	u16			apicid;
	u16			initial_apicid;
	u16			x86_clflush_size;
	/* number of cores as seen by the OS: */
	u16			booted_cores;
	/* Physical processor id: */
	u16			phys_proc_id;
	/* Logical processor id: */
	u16			logical_proc_id;
	/* Core id: */
	u16			cpu_core_id;
	/* Index into per_cpu list: */
	u16			cpu_index;
	u32			microcode;
	/* Address space bits used by the cache internally */
	u8			x86_cache_bits;
	unsigned		initialized : 1;
	RH_KABI_AUX_EMBED(cpuinfo_x86_extended);
} __randomize_layout;

struct cpuid_regs {
	u32 eax, ebx, ecx, edx;
};

enum cpuid_regs_idx {
	CPUID_EAX = 0,
	CPUID_EBX,
	CPUID_ECX,
	CPUID_EDX,
};

#define X86_VENDOR_INTEL	0
#define X86_VENDOR_CYRIX	1
#define X86_VENDOR_AMD		2
#define X86_VENDOR_UMC		3
#define X86_VENDOR_CENTAUR	5
#define X86_VENDOR_TRANSMETA	7
#define X86_VENDOR_NSC		8
#define X86_VENDOR_HYGON	9
#define X86_VENDOR_NUM		10

#define X86_VENDOR_UNKNOWN	0xff

/*
 * capabilities of CPUs
 */
extern struct cpuinfo_x86	boot_cpu_data;
extern struct cpuinfo_x86	new_cpu_data;

extern struct x86_hw_tss	doublefault_tss;
extern __u32			cpu_caps_cleared[NCAPINTS + NBUGINTS];
extern __u32			cpu_caps_set[NCAPINTS + NBUGINTS];

#ifdef CONFIG_SMP
DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
#define cpu_data(cpu)		per_cpu(cpu_info, cpu)
#else
#define cpu_info		boot_cpu_data
#define cpu_data(cpu)		boot_cpu_data
#endif

extern const struct seq_operations cpuinfo_op;

#define cache_line_size()	(boot_cpu_data.x86_cache_alignment)

extern void cpu_detect(struct cpuinfo_x86 *c);

static inline unsigned long long l1tf_pfn_limit(void)
{
	return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
}

extern void early_cpu_init(void);
extern void identify_boot_cpu(void);
extern void identify_secondary_cpu(struct cpuinfo_x86 *);
extern void print_cpu_info(struct cpuinfo_x86 *);
void print_cpu_msr(struct cpuinfo_x86 *);

#ifdef CONFIG_X86_32
extern int have_cpuid_p(void);
#else
static inline int have_cpuid_p(void)
{
	return 1;
}
#endif
static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
				unsigned int *ecx, unsigned int *edx)
{
	/* ecx is often an input as well as an output. */
	asm volatile("cpuid"
	    : "=a" (*eax),
	      "=b" (*ebx),
	      "=c" (*ecx),
	      "=d" (*edx)
	    : "0" (*eax), "2" (*ecx)
	    : "memory");
}

#define native_cpuid_reg(reg)					\
static inline unsigned int native_cpuid_##reg(unsigned int op)	\
{								\
	unsigned int eax = op, ebx, ecx = 0, edx;		\
								\
	native_cpuid(&eax, &ebx, &ecx, &edx);			\
								\
	return reg;						\
}

/*
 * Native CPUID functions returning a single datum.
 */
native_cpuid_reg(eax)
native_cpuid_reg(ebx)
native_cpuid_reg(ecx)
native_cpuid_reg(edx)

/*
 * Friendlier CR3 helpers.
 */
static inline unsigned long read_cr3_pa(void)
{
	return __read_cr3() & CR3_ADDR_MASK;
}

static inline unsigned long native_read_cr3_pa(void)
{
	return __native_read_cr3() & CR3_ADDR_MASK;
}

static inline void load_cr3(pgd_t *pgdir)
{
	write_cr3(__sme_pa(pgdir));
}

/*
 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
 * unrelated to the task-switch mechanism:
 */
#ifdef CONFIG_X86_32
/* This is the TSS defined by the hardware. */
struct x86_hw_tss {
	unsigned short		back_link, __blh;
	unsigned long		sp0;
	unsigned short		ss0, __ss0h;
	unsigned long		sp1;

/*
	 * We don't use ring 1, so ss1 is a convenient scratch space in
	 * the same cacheline as sp0.  We use ss1 to cache the value in
	 * MSR_IA32_SYSENTER_CS.  When we context switch
	 * MSR_IA32_SYSENTER_CS, we first check if the new value being
	 * written matches ss1, and, if it's not, then we wrmsr the new
	 * value and update ss1.
	 *
	 * The only reason we context switch MSR_IA32_SYSENTER_CS is
	 * that we set it to zero in vm86 tasks to avoid corrupting the
	 * stack if we were to go through the sysenter path from vm86
	 * mode.
	 */
	unsigned short		ss1;	/* MSR_IA32_SYSENTER_CS */

unsigned short		__ss1h;
	unsigned long		sp2;
	unsigned short		ss2, __ss2h;
	unsigned long		__cr3;
	unsigned long		ip;
	unsigned long		flags;
	unsigned long		ax;
	unsigned long		cx;
	unsigned long		dx;
	unsigned long		bx;
	unsigned long		sp;
	unsigned long		bp;
	unsigned long		si;
	unsigned long		di;
	unsigned short		es, __esh;
	unsigned short		cs, __csh;
	unsigned short		ss, __ssh;
	unsigned short		ds, __dsh;
	unsigned short		fs, __fsh;
	unsigned short		gs, __gsh;
	unsigned short		ldt, __ldth;
	unsigned short		trace;
	unsigned short		io_bitmap_base;

} __attribute__((packed));
#else
struct x86_hw_tss {
	u32			reserved1;
	u64			sp0;

/*
	 * We store cpu_current_top_of_stack in sp1 so it's always accessible.
	 * Linux does not use ring 1, so sp1 is not otherwise needed.
	 */
	u64			sp1;

/*
	 * Since Linux does not use ring 2, the 'sp2' slot is unused by
	 * hardware.  entry_SYSCALL_64 uses it as scratch space to stash
	 * the user RSP value.
	 */
	u64			sp2;

u64			reserved2;
	u64			ist[7];
	u32			reserved3;
	u32			reserved4;
	u16			reserved5;
	u16			io_bitmap_base;

} __attribute__((packed));
#endif

/*
 * IO-bitmap sizes:
 */
#define IO_BITMAP_BITS			65536
#define IO_BITMAP_BYTES			(IO_BITMAP_BITS/8)
#define IO_BITMAP_LONGS			(IO_BITMAP_BYTES/sizeof(long))
#define IO_BITMAP_OFFSET		(offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
#define INVALID_IO_BITMAP_OFFSET	0x8000

struct entry_stack {
	unsigned long		words[64];
};

struct entry_stack_page {
	struct entry_stack stack;
} __aligned(PAGE_SIZE);

struct tss_struct {
	/*
	 * The fixed hardware portion.  This must not cross a page boundary
	 * at risk of violating the SDM's advice and potentially triggering
	 * errata.
	 */
	struct x86_hw_tss	x86_tss;

/*
	 * The extra 1 is there because the CPU will access an
	 * additional byte beyond the end of the IO permission
	 * bitmap. The extra byte must be all 1 bits, and must
	 * be within the limit.
	 */
	unsigned long		io_bitmap[IO_BITMAP_LONGS + 1];
} __aligned(PAGE_SIZE);

DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);

/*
 * sizeof(unsigned long) coming from an extra "long" at the end
 * of the iobitmap.
 *
 * -1? seg base+limit should be pointing to the address of the
 * last valid byte
 */
#define __KERNEL_TSS_LIMIT	\
	(IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)

/* Per CPU interrupt stacks */
struct irq_stack {
	char		stack[IRQ_STACK_SIZE];
} __aligned(IRQ_STACK_SIZE);

DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);

#ifdef CONFIG_X86_32
DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
#else
/* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
#define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
#endif

#ifdef CONFIG_X86_64
struct fixed_percpu_data {
	/*
	 * GCC hardcodes the stack canary as %gs:40.  Since the
	 * irq_stack is the object at %gs:0, we reserve the bottom
	 * 48 bytes of the irq stack for the canary.
	 */
	char		gs_base[40];
	unsigned long	stack_canary;
};

DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
DECLARE_INIT_PER_CPU(fixed_percpu_data);

static inline unsigned long cpu_kernelmode_gs_base(int cpu)
{
	return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
}

DECLARE_PER_CPU(unsigned int, irq_count);
extern asmlinkage void entry_SYSCALL32_ignore(void);

/* Save actual FS/GS selectors and bases to current->thread */
void current_save_fsgs(void);
#else	/* X86_64 */
#ifdef CONFIG_STACKPROTECTOR
/*
 * Make sure stack canary segment base is cached-aligned:
 *   "For Intel Atom processors, avoid non zero segment base address
 *    that is not aligned to cache line boundary at all cost."
 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 */
struct stack_canary {
	char __pad[20];		/* canary at %gs:20 */
	unsigned long canary;
};
DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
#endif
/* Per CPU softirq stack pointer */
DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr);
#endif	/* X86_64 */

struct perf_event;

typedef struct {
	unsigned long		seg;
} mm_segment_t;

struct thread_struct {
	/* Cached TLS descriptors: */
	struct desc_struct	tls_array[GDT_ENTRY_TLS_ENTRIES];
#ifdef CONFIG_X86_32
	unsigned long		sp0;
#endif
	unsigned long		sp;
#ifdef CONFIG_X86_32
	unsigned long		sysenter_cs;
#else
	unsigned short		es;
	unsigned short		ds;
	unsigned short		fsindex;
	unsigned short		gsindex;
#endif

#ifdef CONFIG_X86_64
	unsigned long		fsbase;
	unsigned long		gsbase;
#else
	/*
	 * XXX: this could presumably be unsigned short.  Alternatively,
	 * 32-bit kernels could be taught to use fsindex instead.
	 */
	unsigned long fs;
	unsigned long gs;
#endif

/* Save middle states of ptrace breakpoints */
	struct perf_event	*ptrace_bps[HBP_NUM];
	/* Debug status used for traps, single steps, etc... */
	unsigned long           debugreg6;
	/* Keep track of the exact dr7 value set by the user */
	unsigned long           ptrace_dr7;
	/* Fault info: */
	unsigned long		cr2;
	unsigned long		trap_nr;
	unsigned long		error_code;
#ifdef CONFIG_VM86
	/* Virtual 86 mode info */
	struct vm86		*vm86;
#endif
	/* IO permissions: */
	unsigned long		*io_bitmap_ptr;
	unsigned long		iopl;
	/* Max allowed port in the bitmap, in bytes: */
	unsigned		io_bitmap_max;

mm_segment_t		addr_limit;

unsigned int		sig_on_uaccess_err:1;
	unsigned int		uaccess_err:1;	/* uaccess failed */

/* Floating point and extended processor state */
	struct fpu		fpu;
	/*
	 * WARNING: 'fpu' is dynamically-sized.  It *MUST* be at
	 * the end.
	 */
};

extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size);

static inline void arch_thread_struct_whitelist(unsigned long *offset,
						unsigned long *size)
{
	fpu_thread_struct_whitelist(offset, size);
}

/*
 * Thread-synchronous status.
 *
 * This is different from the flags in that nobody else
 * ever touches our thread-synchronous status, so we don't
 * have to worry about atomic accesses.
 */
#define TS_COMPAT		0x0002	/* 32bit syscall active (64BIT)*/

/*
 * Set IOPL bits in EFLAGS from given mask
 */
static inline void native_set_iopl_mask(unsigned mask)
{
#ifdef CONFIG_X86_32
	unsigned int reg;

asm volatile ("pushfl;"
		      "popl %0;"
		      "andl %1, %0;"
		      "orl %2, %0;"
		      "pushl %0;"
		      "popfl"
		      : "=&r" (reg)
		      : "i" (~X86_EFLAGS_IOPL), "r" (mask));
#endif
}

static inline void
native_load_sp0(unsigned long sp0)
{
	this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
}

static __always_inline void native_swapgs(void)
{
#ifdef CONFIG_X86_64
	asm volatile("swapgs" ::: "memory");
#endif
}

static inline unsigned long current_top_of_stack(void)
{
	/*
	 *  We can't read directly from tss.sp0: sp0 on x86_32 is special in
	 *  and around vm86 mode and sp0 on x86_64 is special because of the
	 *  entry trampoline.
	 */
	return this_cpu_read_stable(cpu_current_top_of_stack);
}

static inline bool on_thread_stack(void)
{
	return (unsigned long)(current_top_of_stack() -
			       current_stack_pointer) < THREAD_SIZE;
}

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define __cpuid			native_cpuid

static inline void load_sp0(unsigned long sp0)
{
	native_load_sp0(sp0);
}

#define set_iopl_mask native_set_iopl_mask
#endif /* CONFIG_PARAVIRT */

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

unsigned long get_wchan(struct task_struct *p);

/*
 * Generic CPUID function
 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 * resulting in stale register contents being returned.
 */
static inline void cpuid(unsigned int op,
			 unsigned int *eax, unsigned int *ebx,
			 unsigned int *ecx, unsigned int *edx)
{
	*eax = op;
	*ecx = 0;
	__cpuid(eax, ebx, ecx, edx);
}

/* Some CPUID calls want 'count' to be placed in ecx */
static inline void cpuid_count(unsigned int op, int count,
			       unsigned int *eax, unsigned int *ebx,
			       unsigned int *ecx, unsigned int *edx)
{
	*eax = op;
	*ecx = count;
	__cpuid(eax, ebx, ecx, edx);
}

/*
 * CPUID functions returning a single datum
 */
static inline unsigned int cpuid_eax(unsigned int op)
{
	unsigned int eax, ebx, ecx, edx;

cpuid(op, &eax, &ebx, &ecx, &edx);

return eax;
}

static inline unsigned int cpuid_ebx(unsigned int op)
{
	unsigned int eax, ebx, ecx, edx;

cpuid(op, &eax, &ebx, &ecx, &edx);

return ebx;
}

static inline unsigned int cpuid_ecx(unsigned int op)
{
	unsigned int eax, ebx, ecx, edx;

cpuid(op, &eax, &ebx, &ecx, &edx);

return ecx;
}

static inline unsigned int cpuid_edx(unsigned int op)
{
	unsigned int eax, ebx, ecx, edx;

cpuid(op, &eax, &ebx, &ecx, &edx);

return edx;
}

extern void select_idle_routine(const struct cpuinfo_x86 *c);
extern void amd_e400_c1e_apic_setup(void);

extern unsigned long		boot_option_idle_override;

enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
			 IDLE_POLL};

extern void enable_sep_cpu(void);
extern int sysenter_setup(void);

void early_trap_pf_init(void);

/* Defined in head.S */
extern struct desc_ptr		early_gdt_descr;

extern void switch_to_new_gdt(int);
extern void load_direct_gdt(int);
extern void load_fixmap_gdt(int);
extern void load_percpu_segment(int);
extern void cpu_init(void);
extern void cpu_init_secondary(void);
extern void cpu_init_exception_handling(void);
extern void cr4_init(void);

static inline unsigned long get_debugctlmsr(void)
{
	unsigned long debugctlmsr = 0;

#ifndef CONFIG_X86_DEBUGCTLMSR
	if (boot_cpu_data.x86 < 6)
		return 0;
#endif
	rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);

return debugctlmsr;
}

static inline void update_debugctlmsr(unsigned long debugctlmsr)
{
#ifndef CONFIG_X86_DEBUGCTLMSR
	if (boot_cpu_data.x86 < 6)
		return;
#endif
	wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
}

extern void set_task_blockstep(struct task_struct *task, bool on);

/* Boot loader type from the setup header: */
extern int			bootloader_type;
extern int			bootloader_version;

extern char			ignore_fpu_irq;

#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH

#ifdef CONFIG_X86_32
# define BASE_PREFETCH		""
# define ARCH_HAS_PREFETCH
#else
# define BASE_PREFETCH		"prefetcht0 %P1"
#endif

/*
 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 *
 * It's not worth to care about 3dnow prefetches for the K6
 * because they are microcoded there and very slow.
 */
static inline void prefetch(const void *x)
{
	alternative_input(BASE_PREFETCH, "prefetchnta %P1",
			  X86_FEATURE_XMM,
			  "m" (*(const char *)x));
}

/*
 * 3dnow prefetch to get an exclusive cache line.
 * Useful for spinlocks to avoid one state transition in the
 * cache coherency protocol:
 */
static inline void prefetchw(const void *x)
{
	alternative_input(BASE_PREFETCH, "prefetchw %P1",
			  X86_FEATURE_3DNOWPREFETCH,
			  "m" (*(const char *)x));
}

static inline void spin_lock_prefetch(const void *x)
{
	prefetchw(x);
}

#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
			   TOP_OF_KERNEL_STACK_PADDING)

#define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))

#define task_pt_regs(task) \
({									\
	unsigned long __ptr = (unsigned long)task_stack_page(task);	\
	__ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;		\
	((struct pt_regs *)__ptr) - 1;					\
})

#ifdef CONFIG_X86_32
/*
 * User space process size: 3GB (default).
 */
#define IA32_PAGE_OFFSET	PAGE_OFFSET
#define TASK_SIZE		PAGE_OFFSET
#define TASK_SIZE_LOW		TASK_SIZE
#define TASK_SIZE_MAX		TASK_SIZE
#define DEFAULT_MAP_WINDOW	TASK_SIZE
#define STACK_TOP		TASK_SIZE
#define STACK_TOP_MAX		STACK_TOP

#define INIT_THREAD  {							  \
	.sp0			= TOP_OF_INIT_STACK,			  \
	.sysenter_cs		= __KERNEL_CS,				  \
	.io_bitmap_ptr		= NULL,					  \
	.addr_limit		= KERNEL_DS,				  \
}

#define KSTK_ESP(task)		(task_pt_regs(task)->sp)

#else
/*
 * User space process size.  This is the first address outside the user range.
 * There are a few constraints that determine this:
 *
 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical
 * address, then that syscall will enter the kernel with a
 * non-canonical return address, and SYSRET will explode dangerously.
 * We avoid this particular problem by preventing anything executable
 * from being mapped at the maximum canonical address.
 *
 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the
 * CPUs malfunction if they execute code from the highest canonical page.
 * They'll speculate right off the end of the canonical space, and
 * bad things happen.  This is worked around in the same way as the
 * Intel problem.
 *
 * With page table isolation enabled, we map the LDT in ... [stay tuned]
 */
#define TASK_SIZE_MAX	((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)

#define DEFAULT_MAP_WINDOW	((1UL << 47) - PAGE_SIZE)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define IA32_PAGE_OFFSET	((current->personality & ADDR_LIMIT_3GB) ? \
					0xc0000000 : 0xFFFFe000)

#define TASK_SIZE_LOW		(test_thread_flag(TIF_ADDR32) ? \
					IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
#define TASK_SIZE		(test_thread_flag(TIF_ADDR32) ? \
					IA32_PAGE_OFFSET : TASK_SIZE_MAX)
#define TASK_SIZE_OF(child)	((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
					IA32_PAGE_OFFSET : TASK_SIZE_MAX)

#define STACK_TOP		TASK_SIZE_LOW
#define STACK_TOP_MAX		TASK_SIZE_MAX

#define INIT_THREAD  {						\
	.addr_limit		= KERNEL_DS,			\
}

extern unsigned long KSTK_ESP(struct task_struct *task);

#endif /* CONFIG_X86_64 */

extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
					       unsigned long new_sp);

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define __TASK_UNMAPPED_BASE(task_size)	(PAGE_ALIGN(task_size / 3))
#define TASK_UNMAPPED_BASE		__TASK_UNMAPPED_BASE(TASK_SIZE_LOW)

#define KSTK_EIP(task)		(task_pt_regs(task)->ip)

/* Get/set a process' ability to use the timestamp counter instruction */
#define GET_TSC_CTL(adr)	get_tsc_mode((adr))
#define SET_TSC_CTL(val)	set_tsc_mode((val))

extern int get_tsc_mode(unsigned long adr);
extern int set_tsc_mode(unsigned int val);

DECLARE_PER_CPU(u64, msr_misc_features_shadow);

/* Register/unregister a process' MPX related resource */
#define MPX_ENABLE_MANAGEMENT()	mpx_enable_management()
#define MPX_DISABLE_MANAGEMENT()	mpx_disable_management()

#ifdef CONFIG_X86_INTEL_MPX
extern int mpx_enable_management(void);
extern int mpx_disable_management(void);
#else
static inline int mpx_enable_management(void)
{
	return -EINVAL;
}
static inline int mpx_disable_management(void)
{
	return -EINVAL;
}
#endif /* CONFIG_X86_INTEL_MPX */

extern u16 get_llc_id(unsigned int cpu);

#ifdef CONFIG_CPU_SUP_AMD
extern u32 amd_get_nodes_per_socket(void);
extern u32 amd_get_highest_perf(void);
extern void amd_clear_divider(void);
extern void amd_check_microcode(void);
#else
static inline u32 amd_get_nodes_per_socket(void)	{ return 0; }
static inline u32 amd_get_highest_perf(void)		{ return 0; }
static inline void amd_clear_divider(void)		{ }
static inline void amd_check_microcode(void)		{ }
#endif

#define for_each_possible_hypervisor_cpuid_base(function) \
	for (function = 0x40000000; function < 0x40010000; function += 0x100)

static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
{
	uint32_t base, eax, signature[3];

for_each_possible_hypervisor_cpuid_base(base) {
		cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);

if (!memcmp(sig, signature, 12) &&
		    (leaves == 0 || ((eax - base) >= leaves)))
			return base;
	}

return 0;
}

extern unsigned long arch_align_stack(unsigned long sp);
void free_init_pages(const char *what, unsigned long begin, unsigned long end);
extern void free_kernel_image_pages(const char *what, void *begin, void *end);

void default_idle(void);
#ifdef	CONFIG_XEN
bool xen_set_default_idle(void);
#else
#define xen_set_default_idle 0
#endif

void stop_this_cpu(void *dummy);
void df_debug(struct pt_regs *regs, long error_code);
void microcode_check(struct cpuinfo_x86 *prev_info);
void store_cpu_caps(struct cpuinfo_x86 *info);

enum l1tf_mitigations {
	L1TF_MITIGATION_OFF,
	L1TF_MITIGATION_FLUSH_NOWARN,
	L1TF_MITIGATION_FLUSH,
	L1TF_MITIGATION_FLUSH_NOSMT,
	L1TF_MITIGATION_FULL,
	L1TF_MITIGATION_FULL_FORCE
};

extern enum l1tf_mitigations l1tf_mitigation;

enum mds_mitigations {
	MDS_MITIGATION_OFF,
	MDS_MITIGATION_FULL,
	MDS_MITIGATION_VMWERV,
};

#ifdef CONFIG_X86_SGX
int arch_memory_failure(unsigned long pfn, int flags);
#define arch_memory_failure arch_memory_failure

bool arch_is_platform_page(u64 paddr);
#define arch_is_platform_page arch_is_platform_page
#endif

extern bool gds_ucode_mitigated(void);

#endif /* _ASM_X86_PROCESSOR_H */

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