FM / clock

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/dt-bindings/clock/

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/dt-bindings/clock

Name	Size	Mode	Actions
actions,s900-cmu.h	2699	0644	edit dl rm
alphascale,asm9260.h	2695	0644	edit dl rm
am3.h	5267	0644	edit dl rm
am4.h	5115	0644	edit dl rm
aspeed-clock.h	1601	0644	edit dl rm
at91.h	751	0644	edit dl rm
ath79-clk.h	479	0644	edit dl rm
axg-aoclkc.h	695	0644	edit dl rm
axg-clkc.h	1908	0644	edit dl rm
axis,artpec6-clkctrl.h	1112	0644	edit dl rm
bcm-cygnus.h	3135	0644	edit dl rm
bcm-ns2.h	2915	0644	edit dl rm
bcm-nsp.h	2148	0644	edit dl rm
bcm-sr.h	3882	0644	edit dl rm
bcm281xx.h	2456	0644	edit dl rm
bcm2835-aux.h	635	0644	edit dl rm
bcm2835.h	2026	0644	edit dl rm
bcm21664.h	1984	0644	edit dl rm
berlin2.h	1073	0644	edit dl rm
berlin2q.h	734	0644	edit dl rm
boston-clock.h	313	0644	edit dl rm
clps711x-clock.h	718	0644	edit dl rm
cortina,gemini-clock.h	885	0644	edit dl rm
dm814.h	1938	0644	edit dl rm
dm816.h	2396	0644	edit dl rm
dra7.h	8049	0644	edit dl rm
efm32-cmu.h	1151	0644	edit dl rm
exynos-audss-clk.h	636	0644	edit dl rm
exynos4.h	9234	0644	edit dl rm
exynos7-clk.h	5281	0644	edit dl rm
exynos3250.h	9083	0644	edit dl rm
exynos5250.h	4616	0644	edit dl rm
exynos5260-clk.h	14876	0644	edit dl rm
exynos5410.h	1689	0644	edit dl rm
exynos5420.h	6949	0644	edit dl rm
exynos5433.h	45470	0644	edit dl rm
exynos5440.h	1141	0644	edit dl rm
gxbb-aoclkc.h	2893	0644	edit dl rm
gxbb-clkc.h	3369	0644	edit dl rm
hi3516cv300-clock.h	1668	0644	edit dl rm
hi3519-clock.h	1328	0644	edit dl rm
hi3620-clock.h	4496	0644	edit dl rm
hi3660-clock.h	6954	0644	edit dl rm
hi6220-clock.h	4619	0644	edit dl rm
hip04-clock.h	1137	0644	edit dl rm
histb-clock.h	2594	0644	edit dl rm
hix5hd2-clock.h	2415	0644	edit dl rm
imx1-clock.h	1055	0644	edit dl rm
imx5-clock.h	7212	0644	edit dl rm
imx6qdl-clock.h	9657	0644	edit dl rm
imx6sl-clock.h	5849	0644	edit dl rm
imx6sll-clock.h	6213	0644	edit dl rm
imx6sx-clock.h	9232	0644	edit dl rm
imx6ul-clock.h	8406	0644	edit dl rm
imx7d-clock.h	16241	0644	edit dl rm
imx21-clock.h	2461	0644	edit dl rm
imx27-clock.h	3494	0644	edit dl rm
jz4740-cgu.h	1067	0644	edit dl rm
jz4770-cgu.h	1602	0644	edit dl rm
jz4780-cgu.h	2509	0644	edit dl rm
lpc18xx-ccu.h	2134	0644	edit dl rm
lpc18xx-cgu.h	1142	0644	edit dl rm
lpc32xx-clock.h	1633	0644	edit dl rm
lsi,axm5516-clks.h	974	0644	edit dl rm
marvell,mmp2.h	2061	0644	edit dl rm
marvell,pxa168.h	1693	0644	edit dl rm
marvell,pxa910.h	1637	0644	edit dl rm
marvell,pxa1928.h	1574	0644	edit dl rm
maxim,max77620.h	632	0644	edit dl rm
maxim,max77686.h	648	0644	edit dl rm
maxim,max77802.h	630	0644	edit dl rm
meson8b-clkc.h	2688	0644	edit dl rm
microchip,pic32-clock.h	1150	0644	edit dl rm
mpc512x-clock.h	2275	0644	edit dl rm
mt2701-clk.h	13980	0644	edit dl rm
mt2712-clk.h	12514	0644	edit dl rm
mt6797-clk.h	8578	0644	edit dl rm
mt7622-clk.h	8151	0644	edit dl rm
mt8135-clk.h	5641	0644	edit dl rm
mt8173-clk.h	9393	0644	edit dl rm
nuvoton,npcm7xx-clock.h	1104	0644	edit dl rm
omap4.h	5917	0644	edit dl rm
omap5.h	4883	0644	edit dl rm
oxsemi,ox810se.h	1002	0644	edit dl rm
oxsemi,ox820.h	1203	0644	edit dl rm
pistachio-clk.h	4863	0644	edit dl rm
pxa-clock.h	1715	0644	edit dl rm
qcom,gcc-apq8084.h	12872	0644	edit dl rm
qcom,gcc-ipq806x.h	8574	0644	edit dl rm
qcom,gcc-ipq4019.h	5791	0644	edit dl rm
qcom,gcc-ipq8074.h	12605	0644	edit dl rm
qcom,gcc-mdm9615.h	9549	0644	edit dl rm
qcom,gcc-msm8660.h	7932	0644	edit dl rm
qcom,gcc-msm8916.h	6190	0644	edit dl rm
qcom,gcc-msm8960.h	9342	0644	edit dl rm
qcom,gcc-msm8974.h	12340	0644	edit dl rm
qcom,gcc-msm8994.h	4890	0644	edit dl rm
qcom,gcc-msm8996.h	12706	0644	edit dl rm
qcom,gcc-msm8998.h	7381	0644	edit dl rm
qcom,gcc-sdm845.h	8691	0644	edit dl rm
qcom,lcc-ipq806x.h	899	0644	edit dl rm
qcom,lcc-mdm9615.h	1701	0644	edit dl rm
qcom,lcc-msm8960.h	1616	0644	edit dl rm
qcom,mmcc-apq8084.h	5722	0644	edit dl rm
qcom,mmcc-msm8960.h	4109	0644	edit dl rm
qcom,mmcc-msm8974.h	5223	0644	edit dl rm
qcom,mmcc-msm8996.h	9403	0644	edit dl rm
qcom,rpmcc.h	3918	0644	edit dl rm
qcom,rpmh.h	556	0644	edit dl rm
qcom,videocc-sdm845.h	934	0644	edit dl rm
r7s72100-clock.h	2832	0644	edit dl rm
r8a73a4-clock.h	1627	0644	edit dl rm
r8a7740-clock.h	1992	0644	edit dl rm
r8a7743-cpg-mssr.h	1269	0644	edit dl rm
r8a7745-cpg-mssr.h	1298	0644	edit dl rm
r8a7778-clock.h	1855	0644	edit dl rm
r8a7779-clock.h	1647	0644	edit dl rm
r8a7790-clock.h	4399	0644	edit dl rm
r8a7790-cpg-mssr.h	1531	0644	edit dl rm
r8a7791-clock.h	4451	0644	edit dl rm
r8a7791-cpg-mssr.h	1416	0644	edit dl rm
r8a7792-clock.h	2568	0644	edit dl rm
r8a7792-cpg-mssr.h	1269	0644	edit dl rm
r8a7793-clock.h	4579	0644	edit dl rm
r8a7793-cpg-mssr.h	1416	0644	edit dl rm
r8a7794-clock.h	3740	0644	edit dl rm
r8a7794-cpg-mssr.h	1387	0644	edit dl rm
r8a7795-cpg-mssr.h	2073	0644	edit dl rm
r8a7796-cpg-mssr.h	2066	0644	edit dl rm
r8a77470-cpg-mssr.h	992	0644	edit dl rm
r8a77965-cpg-mssr.h	1821	0644	edit dl rm
r8a77970-cpg-mssr.h	1498	0644	edit dl rm
r8a77980-cpg-mssr.h	1498	0644	edit dl rm
r8a77990-cpg-mssr.h	1806	0644	edit dl rm
r8a77995-cpg-mssr.h	1739	0644	edit dl rm
renesas-cpg-mssr.h	542	0644	edit dl rm
rk3036-cru.h	4584	0644	edit dl rm
rk3066a-cru.h	1068	0644	edit dl rm
rk3128-cru.h	6691	0644	edit dl rm
rk3188-cru-common.h	6271	0644	edit dl rm
rk3188-cru.h	1435	0644	edit dl rm
rk3228-cru.h	7096	0644	edit dl rm
rk3288-cru.h	9424	0644	edit dl rm
rk3328-cru.h	9792	0644	edit dl rm
rk3368-cru.h	9508	0644	edit dl rm
rk3399-cru.h	20042	0644	edit dl rm
rockchip,rk808.h	244	0644	edit dl rm
rv1108-cru.h	8959	0644	edit dl rm
s3c2410.h	1475	0644	edit dl rm
s3c2412.h	1755	0644	edit dl rm
s3c2443.h	2257	0644	edit dl rm
s5pv210-audss.h	831	0644	edit dl rm
s5pv210.h	5413	0644	edit dl rm
samsung,s2mps11.h	649	0644	edit dl rm
samsung,s3c64xx-clock.h	4212	0644	edit dl rm
sh73a0-clock.h	2100	0644	edit dl rm
sprd,sc9860-clk.h	10686	0644	edit dl rm
ste-ab8500.h	279	0644	edit dl rm
stih407-clks.h	2076	0644	edit dl rm
stih410-clks.h	568	0644	edit dl rm
stih416-clks.h	309	0644	edit dl rm
stih418-clks.h	834	0644	edit dl rm
stm32fx-clock.h	1287	0644	edit dl rm
stm32h7-clks.h	3187	0644	edit dl rm
stm32mp1-clks.h	4724	0644	edit dl rm
stratix10-clock.h	2520	0644	edit dl rm
sun4i-a10-ccu.h	5774	0644	edit dl rm
sun4i-a10-pll2.h	2281	0644	edit dl rm
sun5i-ccu.h	2633	0644	edit dl rm
sun6i-a31-ccu.h	5504	0644	edit dl rm
sun7i-a20-ccu.h	2206	0644	edit dl rm
sun8i-a23-a33-ccu.h	4030	0644	edit dl rm
sun8i-a83t-ccu.h	4178	0644	edit dl rm
sun8i-de2.h	376	0644	edit dl rm
sun8i-h3-ccu.h	4563	0644	edit dl rm
sun8i-r-ccu.h	2376	0644	edit dl rm
sun8i-r40-ccu.h	5483	0644	edit dl rm
sun8i-v3s-ccu.h	3532	0644	edit dl rm
sun9i-a80-ccu.h	4759	0644	edit dl rm
sun9i-a80-de.h	2862	0644	edit dl rm
sun9i-a80-usb.h	2386	0644	edit dl rm
sun50i-a64-ccu.h	4195	0644	edit dl rm
sun50i-h6-ccu.h	2964	0644	edit dl rm
sun50i-h6-r-ccu.h	510	0644	edit dl rm
tegra20-car.h	4605	0644	edit dl rm
tegra30-car.h	7210	0644	edit dl rm
tegra114-car.h	8276	0644	edit dl rm
tegra124-car-common.h	8690	0644	edit dl rm
tegra124-car.h	492	0644	edit dl rm
tegra186-clock.h	40611	0644	edit dl rm
tegra194-clock.h	11456	0644	edit dl rm
tegra210-car.h	10292	0644	edit dl rm
vf610-clock.h	6414	0644	edit dl rm
zx296702-clock.h	6179	0644	edit dl rm
zx296718-clock.h	3981	0644	edit dl rm

Edit: /usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/dt-bindings/clock/exynos5420.h (6949B)

/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Author: Andrzej Hajda <a.hajda@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Device Tree binding constants for Exynos5420 clock controller.
*/

#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H

/* core clocks */
#define CLK_FIN_PLL		1
#define CLK_FOUT_APLL		2
#define CLK_FOUT_CPLL		3
#define CLK_FOUT_DPLL		4
#define CLK_FOUT_EPLL		5
#define CLK_FOUT_RPLL		6
#define CLK_FOUT_IPLL		7
#define CLK_FOUT_SPLL		8
#define CLK_FOUT_VPLL		9
#define CLK_FOUT_MPLL		10
#define CLK_FOUT_BPLL		11
#define CLK_FOUT_KPLL		12
#define CLK_ARM_CLK		13
#define CLK_KFC_CLK		14

/* gate for special clocks (sclk) */
#define CLK_SCLK_UART0		128
#define CLK_SCLK_UART1		129
#define CLK_SCLK_UART2		130
#define CLK_SCLK_UART3		131
#define CLK_SCLK_MMC0		132
#define CLK_SCLK_MMC1		133
#define CLK_SCLK_MMC2		134
#define CLK_SCLK_SPI0		135
#define CLK_SCLK_SPI1		136
#define CLK_SCLK_SPI2		137
#define CLK_SCLK_I2S1		138
#define CLK_SCLK_I2S2		139
#define CLK_SCLK_PCM1		140
#define CLK_SCLK_PCM2		141
#define CLK_SCLK_SPDIF		142
#define CLK_SCLK_HDMI		143
#define CLK_SCLK_PIXEL		144
#define CLK_SCLK_DP1		145
#define CLK_SCLK_MIPI1		146
#define CLK_SCLK_FIMD1		147
#define CLK_SCLK_MAUDIO0	148
#define CLK_SCLK_MAUPCM0	149
#define CLK_SCLK_USBD300	150
#define CLK_SCLK_USBD301	151
#define CLK_SCLK_USBPHY300	152
#define CLK_SCLK_USBPHY301	153
#define CLK_SCLK_UNIPRO		154
#define CLK_SCLK_PWM		155
#define CLK_SCLK_GSCL_WA	156
#define CLK_SCLK_GSCL_WB	157
#define CLK_SCLK_HDMIPHY	158
#define CLK_MAU_EPLL		159
#define CLK_SCLK_HSIC_12M	160
#define CLK_SCLK_MPHY_IXTAL24	161

/* gate clocks */
#define CLK_UART0		257
#define CLK_UART1		258
#define CLK_UART2		259
#define CLK_UART3		260
#define CLK_I2C0		261
#define CLK_I2C1		262
#define CLK_I2C2		263
#define CLK_I2C3		264
#define CLK_USI0		265
#define CLK_USI1		266
#define CLK_USI2		267
#define CLK_USI3		268
#define CLK_I2C_HDMI		269
#define CLK_TSADC		270
#define CLK_SPI0		271
#define CLK_SPI1		272
#define CLK_SPI2		273
#define CLK_KEYIF		274
#define CLK_I2S1		275
#define CLK_I2S2		276
#define CLK_PCM1		277
#define CLK_PCM2		278
#define CLK_PWM			279
#define CLK_SPDIF		280
#define CLK_USI4		281
#define CLK_USI5		282
#define CLK_USI6		283
#define CLK_ACLK66_PSGEN	300
#define CLK_CHIPID		301
#define CLK_SYSREG		302
#define CLK_TZPC0		303
#define CLK_TZPC1		304
#define CLK_TZPC2		305
#define CLK_TZPC3		306
#define CLK_TZPC4		307
#define CLK_TZPC5		308
#define CLK_TZPC6		309
#define CLK_TZPC7		310
#define CLK_TZPC8		311
#define CLK_TZPC9		312
#define CLK_HDMI_CEC		313
#define CLK_SECKEY		314
#define CLK_MCT			315
#define CLK_WDT			316
#define CLK_RTC			317
#define CLK_TMU			318
#define CLK_TMU_GPU		319
#define CLK_PCLK66_GPIO		330
#define CLK_ACLK200_FSYS2	350
#define CLK_MMC0		351
#define CLK_MMC1		352
#define CLK_MMC2		353
#define CLK_SROMC		354
#define CLK_UFS			355
#define CLK_ACLK200_FSYS	360
#define CLK_TSI			361
#define CLK_PDMA0		362
#define CLK_PDMA1		363
#define CLK_RTIC		364
#define CLK_USBH20		365
#define CLK_USBD300		366
#define CLK_USBD301		367
#define CLK_ACLK400_MSCL	380
#define CLK_MSCL0		381
#define CLK_MSCL1		382
#define CLK_MSCL2		383
#define CLK_SMMU_MSCL0		384
#define CLK_SMMU_MSCL1		385
#define CLK_SMMU_MSCL2		386
#define CLK_ACLK333		400
#define CLK_MFC			401
#define CLK_SMMU_MFCL		402
#define CLK_SMMU_MFCR		403
#define CLK_ACLK200_DISP1	410
#define CLK_DSIM1		411
#define CLK_DP1			412
#define CLK_HDMI		413
#define CLK_ACLK300_DISP1	420
#define CLK_FIMD1		421
#define CLK_SMMU_FIMD1M0	422
#define CLK_SMMU_FIMD1M1	423
#define CLK_ACLK166		430
#define CLK_MIXER		431
#define CLK_ACLK266		440
#define CLK_ROTATOR		441
#define CLK_MDMA1		442
#define CLK_SMMU_ROTATOR	443
#define CLK_SMMU_MDMA1		444
#define CLK_ACLK300_JPEG	450
#define CLK_JPEG		451
#define CLK_JPEG2		452
#define CLK_SMMU_JPEG		453
#define CLK_SMMU_JPEG2		454
#define CLK_ACLK300_GSCL	460
#define CLK_SMMU_GSCL0		461
#define CLK_SMMU_GSCL1		462
#define CLK_GSCL_WA		463
#define CLK_GSCL_WB		464
#define CLK_GSCL0		465
#define CLK_GSCL1		466
#define CLK_FIMC_3AA		467
#define CLK_ACLK266_G2D		470
#define CLK_SSS			471
#define CLK_SLIM_SSS		472
#define CLK_MDMA0		473
#define CLK_ACLK333_G2D		480
#define CLK_G2D			481
#define CLK_ACLK333_432_GSCL	490
#define CLK_SMMU_3AA		491
#define CLK_SMMU_FIMCL0		492
#define CLK_SMMU_FIMCL1		493
#define CLK_SMMU_FIMCL3		494
#define CLK_FIMC_LITE3		495
#define CLK_FIMC_LITE0		496
#define CLK_FIMC_LITE1		497
#define CLK_ACLK_G3D		500
#define CLK_G3D			501
#define CLK_SMMU_MIXER		502
#define CLK_SMMU_G2D		503
#define CLK_SMMU_MDMA0		504
#define CLK_MC			505
#define CLK_TOP_RTC		506
#define CLK_SCLK_UART_ISP	510
#define CLK_SCLK_SPI0_ISP	511
#define CLK_SCLK_SPI1_ISP	512
#define CLK_SCLK_PWM_ISP	513
#define CLK_SCLK_ISP_SENSOR0	514
#define CLK_SCLK_ISP_SENSOR1	515
#define CLK_SCLK_ISP_SENSOR2	516
#define CLK_ACLK432_SCALER	517
#define CLK_ACLK432_CAM		518
#define CLK_ACLK_FL1550_CAM	519
#define CLK_ACLK550_CAM		520

/* mux clocks */
#define CLK_MOUT_HDMI		640
#define CLK_MOUT_G3D		641
#define CLK_MOUT_VPLL		642
#define CLK_MOUT_MAUDIO0	643
#define CLK_MOUT_USER_ACLK333	644
#define CLK_MOUT_SW_ACLK333	645
#define CLK_MOUT_USER_ACLK200_DISP1	646
#define CLK_MOUT_SW_ACLK200	647
#define CLK_MOUT_USER_ACLK300_DISP1     648
#define CLK_MOUT_SW_ACLK300     649
#define CLK_MOUT_USER_ACLK400_DISP1     650
#define CLK_MOUT_SW_ACLK400     651
#define CLK_MOUT_USER_ACLK300_GSCL	652
#define CLK_MOUT_SW_ACLK300_GSCL	653
#define CLK_MOUT_MCLK_CDREX	654
#define CLK_MOUT_BPLL		655
#define CLK_MOUT_MX_MSPLL_CCORE	656
#define CLK_MOUT_EPLL		657
#define CLK_MOUT_MAU_EPLL	658
#define CLK_MOUT_USER_MAU_EPLL	659

/* divider clocks */
#define CLK_DOUT_PIXEL		768
#define CLK_DOUT_ACLK400_WCORE	769
#define CLK_DOUT_ACLK400_ISP	770
#define CLK_DOUT_ACLK400_MSCL	771
#define CLK_DOUT_ACLK200	772
#define CLK_DOUT_ACLK200_FSYS2	773
#define CLK_DOUT_ACLK100_NOC	774
#define CLK_DOUT_PCLK200_FSYS	775
#define CLK_DOUT_ACLK200_FSYS	776
#define CLK_DOUT_ACLK333_432_GSCL	777
#define CLK_DOUT_ACLK333_432_ISP	778
#define CLK_DOUT_ACLK66		779
#define CLK_DOUT_ACLK333_432_ISP0	780
#define CLK_DOUT_ACLK266	781
#define CLK_DOUT_ACLK166	782
#define CLK_DOUT_ACLK333	783
#define CLK_DOUT_ACLK333_G2D	784
#define CLK_DOUT_ACLK266_G2D	785
#define CLK_DOUT_ACLK_G3D	786
#define CLK_DOUT_ACLK300_JPEG	787
#define CLK_DOUT_ACLK300_DISP1	788
#define CLK_DOUT_ACLK300_GSCL	789
#define CLK_DOUT_ACLK400_DISP1	790
#define CLK_DOUT_PCLK_CDREX	791
#define CLK_DOUT_SCLK_CDREX	792
#define CLK_DOUT_ACLK_CDREX1	793
#define CLK_DOUT_CCLK_DREX0	794
#define CLK_DOUT_CLK2X_PHY0	795
#define CLK_DOUT_PCLK_CORE_MEM	796

/* must be greater than maximal clock id */
#define CLK_NR_CLKS		797

#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */

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