FM / reset

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/dt-bindings/reset/

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/dt-bindings/reset

Name	Size	Mode	Actions
altr,rst-mgr-a10.h	2742	0644	edit dl rm
altr,rst-mgr-a10sr.h	1082	0644	edit dl rm
altr,rst-mgr-s10.h	2769	0644	edit dl rm
altr,rst-mgr.h	2279	0644	edit dl rm
amlogic,meson-axg-reset.h	2896	0644	edit dl rm
amlogic,meson-gxbb-reset.h	6549	0644	edit dl rm
amlogic,meson8b-clkc-reset.h	1042	0644	edit dl rm
amlogic,meson8b-reset.h	5779	0644	edit dl rm
axg-aoclkc.h	519	0644	edit dl rm
cortina,gemini-reset.h	1039	0644	edit dl rm
gxbb-aoclkc.h	2866	0644	edit dl rm
hisi,hi6220-resets.h	3229	0644	edit dl rm
imx7-reset.h	1952	0644	edit dl rm
mt2701-resets.h	3099	0644	edit dl rm
mt7622-reset.h	3146	0644	edit dl rm
mt8135-resets.h	2488	0644	edit dl rm
mt8173-resets.h	2407	0644	edit dl rm
oxsemi,ox810se.h	1459	0644	edit dl rm
oxsemi,ox820.h	1490	0644	edit dl rm
pistachio-resets.h	1085	0644	edit dl rm
qcom,gcc-apq8084.h	3381	0644	edit dl rm
qcom,gcc-ipq806x.h	5819	0644	edit dl rm
qcom,gcc-mdm9615.h	4172	0644	edit dl rm
qcom,gcc-msm8660.h	4073	0644	edit dl rm
qcom,gcc-msm8916.h	3333	0644	edit dl rm
qcom,gcc-msm8960.h	4089	0644	edit dl rm
qcom,gcc-msm8974.h	3084	0644	edit dl rm
qcom,mmcc-apq8084.h	1978	0644	edit dl rm
qcom,mmcc-msm8960.h	3112	0644	edit dl rm
qcom,mmcc-msm8974.h	1919	0644	edit dl rm
snps,hsdk-reset.h	446	0644	edit dl rm
stih407-resets.h	2145	0644	edit dl rm
stih415-resets.h	882	0644	edit dl rm
stih416-resets.h	1762	0644	edit dl rm
stm32mp1-resets.h	2491	0644	edit dl rm
sun4i-a10-ccu.h	2595	0644	edit dl rm
sun5i-ccu.h	891	0644	edit dl rm
sun6i-a31-ccu.h	3595	0644	edit dl rm
sun8i-a23-a33-ccu.h	3135	0644	edit dl rm
sun8i-a83t-ccu.h	3256	0644	edit dl rm
sun8i-de2.h	298	0644	edit dl rm
sun8i-h3-ccu.h	3539	0644	edit dl rm
sun8i-r-ccu.h	2284	0644	edit dl rm
sun8i-r40-ccu.h	4157	0644	edit dl rm
sun8i-v3s-ccu.h	2865	0644	edit dl rm
sun9i-a80-ccu.h	3414	0644	edit dl rm
sun9i-a80-de.h	2335	0644	edit dl rm
sun9i-a80-usb.h	2314	0644	edit dl rm
sun50i-a64-ccu.h	3406	0644	edit dl rm
sun50i-h6-ccu.h	1824	0644	edit dl rm
sun50i-h6-r-ccu.h	433	0644	edit dl rm
tegra124-car.h	360	0644	edit dl rm
tegra186-reset.h	8007	0644	edit dl rm
tegra194-reset.h	5536	0644	edit dl rm
tegra210-car.h	405	0644	edit dl rm
ti-syscon.h	1232	0644	edit dl rm

Edit: /usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/dt-bindings/reset/mt8135-resets.h (2488B)

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Flora Fu, MediaTek
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
#define _DT_BINDINGS_RESET_CONTROLLER_MT8135

/* INFRACFG resets */
#define MT8135_INFRA_EMI_REG_RST        0
#define MT8135_INFRA_DRAMC0_A0_RST      1
#define MT8135_INFRA_CCIF0_RST          2
#define MT8135_INFRA_APCIRQ_EINT_RST    3
#define MT8135_INFRA_APXGPT_RST         4
#define MT8135_INFRA_SCPSYS_RST         5
#define MT8135_INFRA_CCIF1_RST          6
#define MT8135_INFRA_PMIC_WRAP_RST      7
#define MT8135_INFRA_KP_RST             8
#define MT8135_INFRA_EMI_RST            32
#define MT8135_INFRA_DRAMC0_RST         34
#define MT8135_INFRA_SMI_RST            35
#define MT8135_INFRA_M4U_RST            36

/*  PERICFG resets */
#define MT8135_PERI_UART0_SW_RST        0
#define MT8135_PERI_UART1_SW_RST        1
#define MT8135_PERI_UART2_SW_RST        2
#define MT8135_PERI_UART3_SW_RST        3
#define MT8135_PERI_IRDA_SW_RST         4
#define MT8135_PERI_PTP_SW_RST          5
#define MT8135_PERI_AP_HIF_SW_RST       6
#define MT8135_PERI_GPCU_SW_RST         7
#define MT8135_PERI_MD_HIF_SW_RST       8
#define MT8135_PERI_NLI_SW_RST          9
#define MT8135_PERI_AUXADC_SW_RST       10
#define MT8135_PERI_DMA_SW_RST          11
#define MT8135_PERI_NFI_SW_RST          14
#define MT8135_PERI_PWM_SW_RST          15
#define MT8135_PERI_THERM_SW_RST        16
#define MT8135_PERI_MSDC0_SW_RST        17
#define MT8135_PERI_MSDC1_SW_RST        18
#define MT8135_PERI_MSDC2_SW_RST        19
#define MT8135_PERI_MSDC3_SW_RST        20
#define MT8135_PERI_I2C0_SW_RST         22
#define MT8135_PERI_I2C1_SW_RST         23
#define MT8135_PERI_I2C2_SW_RST         24
#define MT8135_PERI_I2C3_SW_RST         25
#define MT8135_PERI_I2C4_SW_RST         26
#define MT8135_PERI_I2C5_SW_RST         27
#define MT8135_PERI_I2C6_SW_RST         28
#define MT8135_PERI_USB_SW_RST          29
#define MT8135_PERI_SPI1_SW_RST         33
#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34

#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */

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