FM / mfd

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/linux/mfd/

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/linux/mfd

Name	Size	Mode	Actions
abx500/	-	0755	rm
arizona/	-	0755	rm
da9052/	-	0755	rm
da9055/	-	0755	rm
da9062/	-	0755	rm
da9063/	-	0755	rm
da9150/	-	0755	rm
mt6323/	-	0755	rm
mt6397/	-	0755	rm
pcf50633/	-	0755	rm
samsung/	-	0755	rm
syscon/	-	0755	rm
wm831x/	-	0755	rm
wm8350/	-	0755	rm
wm8994/	-	0755	rm
88pm80x.h	10226	0644	edit dl rm
88pm860x.h	13654	0644	edit dl rm
aat2870.h	4651	0644	edit dl rm
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abx500.h	11980	0644	edit dl rm
ac100.h	6267	0644	edit dl rm
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altera-a10sr.h	3507	0644	edit dl rm
as3711.h	2960	0644	edit dl rm
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asic3.h	12514	0644	edit dl rm
atmel-hlcdc.h	2634	0644	edit dl rm
axp20x.h	17214	0644	edit dl rm
bcm590xx.h	831	0644	edit dl rm
bd9571mwv.h	3712	0644	edit dl rm
core.h	4794	0644	edit dl rm
cros_ec.h	10595	0644	edit dl rm
cros_ec_commands.h	87508	0644	edit dl rm
cros_ec_lpc_mec.h	2838	0644	edit dl rm
cros_ec_lpc_reg.h	1949	0644	edit dl rm
da8xx-cfgchip.h	7501	0644	edit dl rm
da903x.h	7218	0644	edit dl rm
davinci_voicecodec.h	3323	0644	edit dl rm
db8500-prcmu.h	22205	0644	edit dl rm
dbx500-prcmu.h	14681	0644	edit dl rm
dln2.h	3617	0644	edit dl rm
dm355evm_msp.h	2879	0644	edit dl rm
ds1wm.h	817	0644	edit dl rm
ezx-pcap.h	7932	0644	edit dl rm
hi655x-pmic.h	2076	0644	edit dl rm
hi6421-pmic.h	1329	0644	edit dl rm
htc-pasic3.h	1225	0644	edit dl rm
imx25-tsadc.h	4972	0644	edit dl rm
intel_msic.h	16376	0644	edit dl rm
intel_soc_pmic.h	1265	0644	edit dl rm
intel_soc_pmic_bxtwc.h	2053	0644	edit dl rm
ipaq-micro.h	3750	0644	edit dl rm
janz.h	1053	0644	edit dl rm
kempld.h	4260	0644	edit dl rm
lm3533.h	2650	0644	edit dl rm
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lp873x.h	8895	0644	edit dl rm
lp3943.h	2747	0644	edit dl rm
lp8788-isink.h	1218	0644	edit dl rm
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lp87565.h	7862	0644	edit dl rm
lpc_ich.h	1261	0644	edit dl rm
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max8925.h	7350	0644	edit dl rm
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max77693-common.h	1303	0644	edit dl rm
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max77843-private.h	15804	0644	edit dl rm
mc13xxx.h	7872	0644	edit dl rm
mc13783.h	2902	0644	edit dl rm
mc13892.h	938	0644	edit dl rm
mcp.h	1816	0644	edit dl rm
menelaus.h	1284	0644	edit dl rm
motorola-cpcap.h	12797	0644	edit dl rm
mxs-lradc.h	6191	0644	edit dl rm
palmas.h	152645	0644	edit dl rm
qcom_rpm.h	293	0644	edit dl rm
rave-sp.h	1414	0644	edit dl rm
rc5t583.h	10056	0644	edit dl rm
rdc321x.h	591	0644	edit dl rm
retu.h	723	0644	edit dl rm
rk808.h	12807	0644	edit dl rm
rn5t618.h	7519	0644	edit dl rm
rt5033-private.h	8026	0644	edit dl rm
rt5033.h	1243	0644	edit dl rm
si476x-core.h	15606	0644	edit dl rm
si476x-platform.h	6603	0644	edit dl rm
si476x-reports.h	5010	0644	edit dl rm
sky81452.h	990	0644	edit dl rm
smsc.h	2921	0644	edit dl rm
sta2x11-mfd.h	19169	0644	edit dl rm
stm32-lptimer.h	1817	0644	edit dl rm
stm32-timers.h	5784	0644	edit dl rm
stmpe.h	3466	0644	edit dl rm
stw481x.h	1442	0644	edit dl rm
sun4i-gpadc.h	3710	0644	edit dl rm
syscon.h	1443	0644	edit dl rm
t7l66xb.h	817	0644	edit dl rm
tc3589x.h	3999	0644	edit dl rm
tc6387xb.h	516	0644	edit dl rm
tc6393xb.h	1548	0644	edit dl rm
ti-lmu-register.h	7613	0644	edit dl rm
ti-lmu.h	1822	0644	edit dl rm
ti_am335x_tscadc.h	5861	0644	edit dl rm
tmio.h	4098	0644	edit dl rm
tps6105x.h	3099	0644	edit dl rm
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twl.h	26189	0644	edit dl rm
twl4030-audio.h	8741	0644	edit dl rm
twl6040.h	7328	0644	edit dl rm
ucb1x00.h	6728	0644	edit dl rm
viperboard.h	3022	0644	edit dl rm
wl1273-core.h	8496	0644	edit dl rm
wm97xx.h	576	0644	edit dl rm
wm8400-audio.h	71471	0644	edit dl rm
wm8400-private.h	59376	0644	edit dl rm
wm8400.h	1213	0644	edit dl rm

Edit: /usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/linux/mfd/tmio.h (4098B)

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef MFD_TMIO_H
#define MFD_TMIO_H

#include <linux/device.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/mmc/card.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

#define tmio_ioread8(addr) readb(addr)
#define tmio_ioread16(addr) readw(addr)
#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
#define tmio_ioread32(addr) \
	(((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))

#define tmio_iowrite8(val, addr) writeb((val), (addr))
#define tmio_iowrite16(val, addr) writew((val), (addr))
#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
#define tmio_iowrite32(val, addr) \
	do { \
		writew((val),       (addr)); \
		writew((val) >> 16, (addr) + 2); \
	} while (0)

#define sd_config_write8(base, shift, reg, val) \
	tmio_iowrite8((val), (base) + ((reg) << (shift)))
#define sd_config_write16(base, shift, reg, val) \
	tmio_iowrite16((val), (base) + ((reg) << (shift)))
#define sd_config_write32(base, shift, reg, val) \
	do { \
		tmio_iowrite16((val), (base) + ((reg) << (shift)));   \
		tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
	} while (0)

/* tmio MMC platform flags */
/*
 * Some controllers can support a 2-byte block size when the bus width
 * is configured in 4-bit mode.
 */
#define TMIO_MMC_BLKSZ_2BYTES		BIT(1)
/*
 * Some controllers can support SDIO IRQ signalling.
 */
#define TMIO_MMC_SDIO_IRQ		BIT(2)

/* Some features are only available or tested on R-Car Gen2 or later */
#define TMIO_MMC_MIN_RCAR2		BIT(3)

/*
 * Some controllers require waiting for the SD bus to become
 * idle before writing to some registers.
 */
#define TMIO_MMC_HAS_IDLE_WAIT		BIT(4)
/*
 * A GPIO is used for card hotplug detection. We need an extra flag for this,
 * because 0 is a valid GPIO number too, and requiring users to specify
 * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
 */
#define TMIO_MMC_USE_GPIO_CD		BIT(5)

/*
 * Some controllers doesn't have over 0x100 register.
 * it is used to checking accessibility of
 * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
 */
#define TMIO_MMC_HAVE_HIGH_REG		BIT(6)

/*
 * Some controllers have CMD12 automatically
 * issue/non-issue register
 */
#define TMIO_MMC_HAVE_CMD12_CTRL	BIT(7)

/* Controller has some SDIO status bits which must be 1 */
#define TMIO_MMC_SDIO_STATUS_SETBITS	BIT(8)

/*
 * Some controllers have a 32-bit wide data port register
 */
#define TMIO_MMC_32BIT_DATA_PORT	BIT(9)

/*
 * Some controllers allows to set SDx actual clock
 */
#define TMIO_MMC_CLK_ACTUAL		BIT(10)

/* Some controllers have a CBSY bit */
#define TMIO_MMC_HAVE_CBSY		BIT(11)

int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);

struct dma_chan;

/*
 * data for the MMC controller
 */
struct tmio_mmc_data {
	void				*chan_priv_tx;
	void				*chan_priv_rx;
	unsigned int			hclk;
	unsigned long			capabilities;
	unsigned long			capabilities2;
	unsigned long			flags;
	u32				ocr_mask;	/* available voltages */
	unsigned int			cd_gpio;
	int				alignment_shift;
	dma_addr_t			dma_rx_offset;
	unsigned int			max_blk_count;
	unsigned short			max_segs;
	void (*set_pwr)(struct platform_device *host, int state);
	void (*set_clk_div)(struct platform_device *host, int state);
};

/*
 * data for the NAND controller
 */
struct tmio_nand_data {
	struct nand_bbt_descr	*badblock_pattern;
	struct mtd_partition	*partition;
	unsigned int		num_partitions;
	const char *const	*part_parsers;
};

#define FBIO_TMIO_ACC_WRITE	0x7C639300
#define FBIO_TMIO_ACC_SYNC	0x7C639301

struct tmio_fb_data {
	int			(*lcd_set_power)(struct platform_device *fb_dev,
						 bool on);
	int			(*lcd_mode)(struct platform_device *fb_dev,
					    const struct fb_videomode *mode);
	int			num_modes;
	struct fb_videomode	*modes;

/* in mm: size of screen */
	int			height;
	int			width;
};

#endif

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