FM / i2c

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/media/i2c/

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/media/i2c

Name	Size	Mode	Actions
ad9389b.h	789	0644	edit dl rm
adp1653.h	4101	0644	edit dl rm
adv7183.h	1611	0644	edit dl rm
adv7343.h	1988	0644	edit dl rm
adv7393.h	883	0644	edit dl rm
adv7511.h	547	0644	edit dl rm
adv7604.h	4062	0644	edit dl rm
adv7842.h	5556	0644	edit dl rm
ak881x.h	665	0644	edit dl rm
bt819.h	1171	0644	edit dl rm
cs53l32a.h	1196	0644	edit dl rm
cs5345.h	1210	0644	edit dl rm
ir-kbd-i2c.h	1508	0644	edit dl rm
lm3560.h	2554	0644	edit dl rm
lm3646.h	2582	0644	edit dl rm
m5mols.h	1077	0644	edit dl rm
m52790.h	2726	0644	edit dl rm
mt9m032.h	872	0644	edit dl rm
mt9p031.h	310	0644	edit dl rm
mt9t001.h	180	0644	edit dl rm
mt9t112.h	586	0644	edit dl rm
mt9v011.h	384	0644	edit dl rm
mt9v022.h	362	0644	edit dl rm
mt9v032.h	202	0644	edit dl rm
noon010pc30.h	727	0644	edit dl rm
ov772x.h	1541	0644	edit dl rm
ov2659.h	1111	0644	edit dl rm
ov7670.h	615	0644	edit dl rm
ov9650.h	874	0644	edit dl rm
rj54n1cb0c.h	425	0644	edit dl rm
s5c73m3.h	1582	0644	edit dl rm
s5k4ecgx.h	892	0644	edit dl rm
s5k6aa.h	1437	0644	edit dl rm
saa6588.h	1338	0644	edit dl rm
saa7115.h	4789	0644	edit dl rm
saa7127.h	1271	0644	edit dl rm
smiapp.h	2155	0644	edit dl rm
sr030pc30.h	628	0644	edit dl rm
tc358743.h	3322	0644	edit dl rm
tda1997x.h	1078	0644	edit dl rm
ths7303.h	602	0644	edit dl rm
tvaudio.h	1964	0644	edit dl rm
tvp514x.h	2628	0644	edit dl rm
tvp7002.h	1919	0644	edit dl rm
tw9910.h	1071	0644	edit dl rm
uda1342.h	307	0644	edit dl rm
upd64031a.h	1136	0644	edit dl rm
upd64083.h	2069	0644	edit dl rm
wm8775.h	1391	0644	edit dl rm

Edit: /usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/media/i2c/tc358743.h (3322B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * tc358743 - Toshiba HDMI to CSI-2 bridge
 *
 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
 */

/*
 * References (c = chapter, p = page):
 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
 */

#ifndef _TC358743_
#define _TC358743_

enum tc358743_ddc5v_delays {
	DDC5V_DELAY_0_MS,
	DDC5V_DELAY_50_MS,
	DDC5V_DELAY_100_MS,
	DDC5V_DELAY_200_MS,
};

enum tc358743_hdmi_detection_delay {
	HDMI_MODE_DELAY_0_MS,
	HDMI_MODE_DELAY_25_MS,
	HDMI_MODE_DELAY_50_MS,
	HDMI_MODE_DELAY_100_MS,
};

struct tc358743_platform_data {
	/* System clock connected to REFCLK (pin H5) */
	u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */

/* DDC +5V debounce delay to avoid spurious interrupts when the cable
	 * is connected.
	 * Sets DDC5V_MODE in register DDC_CTL.
	 * Default: DDC5V_DELAY_0_MS
	 */
	enum tc358743_ddc5v_delays ddc5v_delay;

bool enable_hdcp;

/*
	 * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO
	 * level to somewhere in the middle (e.g. 300), so it can cover speed
	 * mismatches in input and output ports.
	 */
	u16 fifo_level;

/* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
	u16 pll_prd;
	u16 pll_fbd;

/* CSI
	 * Calculate CSI parameters with REF_02 for the highest resolution your
	 * CSI interface can handle. The driver will adjust the number of CSI
	 * lanes in use according to the pixel clock.
	 *
	 * The values in brackets are calculated with REF_02 when the number of
	 * bps pr lane is 823.5 MHz, and can serve as a starting point.
	 */
	u32 lineinitcnt;	/* (0x00001770) */
	u32 lptxtimecnt;	/* (0x00000005) */
	u32 tclk_headercnt;	/* (0x00001d04) */
	u32 tclk_trailcnt;	/* (0x00000000) */
	u32 ths_headercnt;	/* (0x00000505) */
	u32 twakeup;		/* (0x00004650) */
	u32 tclk_postcnt;	/* (0x00000000) */
	u32 ths_trailcnt;	/* (0x00000004) */
	u32 hstxvregcnt;	/* (0x00000005) */

/* DVI->HDMI detection delay to avoid unnecessary switching between DVI
	 * and HDMI mode.
	 * Sets HDMI_DET_V in register HDMI_DET.
	 * Default: HDMI_MODE_DELAY_0_MS
	 */
	enum tc358743_hdmi_detection_delay hdmi_detection_delay;

/* Reset PHY automatically when TMDS clock goes from DC to AC.
	 * Sets PHY_AUTO_RST2 in register PHY_CTL2.
	 * Default: false
	 */
	bool hdmi_phy_auto_reset_tmds_detected;

/* Reset PHY automatically when TMDS clock passes 21 MHz.
	 * Sets PHY_AUTO_RST3 in register PHY_CTL2.
	 * Default: false
	 */
	bool hdmi_phy_auto_reset_tmds_in_range;

/* Reset PHY automatically when TMDS clock is detected.
	 * Sets PHY_AUTO_RST4 in register PHY_CTL2.
	 * Default: false
	 */
	bool hdmi_phy_auto_reset_tmds_valid;

/* Reset HDMI PHY automatically when hsync period is out of range.
	 * Sets H_PI_RST in register HV_RST.
	 * Default: false
	 */
	bool hdmi_phy_auto_reset_hsync_out_of_range;

/* Reset HDMI PHY automatically when vsync period is out of range.
	 * Sets V_PI_RST in register HV_RST.
	 * Default: false
	 */
	bool hdmi_phy_auto_reset_vsync_out_of_range;
};

/* custom controls */
/* Audio sample rate in Hz */
#define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0)
/* Audio present status */
#define TC358743_CID_AUDIO_PRESENT       (V4L2_CID_USER_TC358743_BASE + 1)

#endif

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