FM / sound

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/sound/

/usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/sound

Name	Size	Mode	Actions
ac97/	-	0755	rm
sof/	-	0755	rm
ac97_codec.h	16173	0644	edit dl rm
aci.h	2458	0644	edit dl rm
acp63_chip_offset_byte.h	30462	0644	edit dl rm
ad1816a.h	4843	0644	edit dl rm
ad1843.h	1516	0644	edit dl rm
adau1373.h	706	0644	edit dl rm
aess.h	1668	0644	edit dl rm
ak4xxx-adda.h	2724	0644	edit dl rm
ak4113.h	10461	0644	edit dl rm
ak4114.h	9773	0644	edit dl rm
ak4117.h	8542	0644	edit dl rm
ak4531_codec.h	2478	0644	edit dl rm
ak4641.h	476	0644	edit dl rm
alc5623.h	536	0644	edit dl rm
asequencer.h	2975	0644	edit dl rm
asound.h	590	0644	edit dl rm
asoundef.h	16403	0644	edit dl rm
compress_driver.h	7987	0644	edit dl rm
control.h	10989	0644	edit dl rm
core.h	16151	0644	edit dl rm
cs35l33.h	888	0644	edit dl rm
cs35l34.h	741	0644	edit dl rm
cs35l35.h	2267	0644	edit dl rm
cs35l36.h	772	0644	edit dl rm
cs35l41.h	34962	0644	edit dl rm
cs42l42.h	35337	0644	edit dl rm
cs42l52.h	592	0644	edit dl rm
cs42l56.h	1046	0644	edit dl rm
cs42l73.h	361	0644	edit dl rm
cs4231-regs.h	7785	0644	edit dl rm
cs4271.h	961	0644	edit dl rm
cs8403.h	8138	0644	edit dl rm
cs8427.h	9954	0644	edit dl rm
da7213.h	1032	0644	edit dl rm
da7218.h	2468	0644	edit dl rm
da7219-aad.h	2263	0644	edit dl rm
da7219.h	998	0644	edit dl rm
da9055.h	707	0644	edit dl rm
designware_i2s.h	1631	0644	edit dl rm
dmaengine_pcm.h	6802	0644	edit dl rm
emu10k1.h	92513	0644	edit dl rm
emu10k1_synth.h	693	0644	edit dl rm
emu8000.h	3333	0644	edit dl rm
emu8000_reg.h	9767	0644	edit dl rm
emux_legacy.h	4811	0644	edit dl rm
emux_synth.h	6948	0644	edit dl rm
es1688.h	2923	0644	edit dl rm
graph_card.h	1070	0644	edit dl rm
gus.h	20119	0644	edit dl rm
hda-mlink.h	6065	0644	edit dl rm
hdaudio.h	24529	0644	edit dl rm
hdaudio_ext.h	6626	0644	edit dl rm
hda_chmap.h	2660	0644	edit dl rm
hda_codec.h	18065	0644	edit dl rm
hda_component.h	2085	0644	edit dl rm
hda_hwdep.h	736	0644	edit dl rm
hda_i915.h	589	0644	edit dl rm
hda_register.h	12172	0644	edit dl rm
hda_regmap.h	6934	0644	edit dl rm
hda_verbs.h	17289	0644	edit dl rm
hdmi-codec.h	3117	0644	edit dl rm
hwdep.h	1926	0644	edit dl rm
i2c.h	2857	0644	edit dl rm
info.h	7941	0644	edit dl rm
initval.h	2484	0644	edit dl rm
intel-dsp-config.h	896	0644	edit dl rm
intel-nhlt.h	3840	0644	edit dl rm
jack.h	3172	0644	edit dl rm
l3.h	524	0644	edit dl rm
max9768.h	729	0644	edit dl rm
max98088.h	1074	0644	edit dl rm
max98090.h	534	0644	edit dl rm
max98095.h	1357	0644	edit dl rm
memalloc.h	3879	0644	edit dl rm
minors.h	3738	0644	edit dl rm
mixer_oss.h	1773	0644	edit dl rm
mpu401.h	3905	0644	edit dl rm
omap-hdmi-audio.h	971	0644	edit dl rm
opl3.h	11909	0644	edit dl rm
opl4.h	459	0644	edit dl rm
pcm-indirect.h	5303	0644	edit dl rm
pcm.h	55007	0644	edit dl rm
pcm_drm_eld.h	183	0644	edit dl rm
pcm_iec958.h	597	0644	edit dl rm
pcm_oss.h	2063	0644	edit dl rm
pcm_params.h	8864	0644	edit dl rm
pt2258.h	513	0644	edit dl rm
pxa2xx-lib.h	2190	0644	edit dl rm
rawmidi.h	5663	0644	edit dl rm
rt286.h	314	0644	edit dl rm
rt298.h	373	0644	edit dl rm
rt1015.h	283	0644	edit dl rm
rt5514.h	399	0644	edit dl rm
rt5659.h	880	0644	edit dl rm
rt5660.h	578	0644	edit dl rm
rt5663.h	476	0644	edit dl rm
rt5665.h	723	0644	edit dl rm
rt5668.h	607	0644	edit dl rm
rt5682.h	862	0644	edit dl rm
rt5682s.h	915	0644	edit dl rm
s3c24xx_uda134x.h	229	0644	edit dl rm
sb.h	10550	0644	edit dl rm
sb16_csp.h	2100	0644	edit dl rm
sdw.h	1667	0644	edit dl rm
seq_device.h	2165	0644	edit dl rm
seq_kernel.h	3378	0644	edit dl rm
seq_midi_emul.h	6757	0644	edit dl rm
seq_midi_event.h	1356	0644	edit dl rm
seq_oss.h	2264	0644	edit dl rm
seq_oss_legacy.h	360	0644	edit dl rm
seq_virmidi.h	2123	0644	edit dl rm
sh_dac_audio.h	441	0644	edit dl rm
sh_fsi.h	693	0644	edit dl rm
simple_card.h	529	0644	edit dl rm
simple_card_utils.h	8816	0644	edit dl rm
snd_wavefront.h	5704	0644	edit dl rm
soc-acpi-intel-match.h	2417	0644	edit dl rm
soc-acpi.h	6675	0644	edit dl rm
soc-card.h	2623	0644	edit dl rm
soc-component.h	20608	0644	edit dl rm
soc-dai.h	21113	0644	edit dl rm
soc-dapm.h	34141	0644	edit dl rm
soc-dpcm.h	5698	0644	edit dl rm
soc-jack.h	3822	0644	edit dl rm
soc-link.h	1172	0644	edit dl rm
soc-topology.h	5882	0644	edit dl rm
soc.h	52841	0644	edit dl rm
sof.h	4031	0644	edit dl rm
soundfont.h	3903	0644	edit dl rm
spear_dma.h	350	0644	edit dl rm
spear_spdif.h	345	0644	edit dl rm
sta32x.h	1015	0644	edit dl rm
sta350.h	1474	0644	edit dl rm
tas2552-plat.h	283	0644	edit dl rm
tas5086.h	210	0644	edit dl rm
tea6330t.h	468	0644	edit dl rm
timer.h	5125	0644	edit dl rm
tlv.h	1627	0644	edit dl rm
tlv320aic32x4.h	1320	0644	edit dl rm
tlv320dac33-plat.h	574	0644	edit dl rm
tpa6130a2-plat.h	291	0644	edit dl rm
uda134x.h	451	0644	edit dl rm
uda1380.h	335	0644	edit dl rm
util_mem.h	1623	0644	edit dl rm
vx_core.h	15055	0644	edit dl rm
wavefront.h	18518	0644	edit dl rm
wm0010.h	466	0644	edit dl rm
wm1250-ev1.h	510	0644	edit dl rm
wm2000.h	479	0644	edit dl rm
wm2200.h	1353	0644	edit dl rm
wm5100.h	1129	0644	edit dl rm
wm8903.h	15377	0644	edit dl rm
wm8904.h	7389	0644	edit dl rm
wm8955.h	442	0644	edit dl rm
wm8960.h	888	0644	edit dl rm
wm8962.h	1694	0644	edit dl rm
wm8993.h	1076	0644	edit dl rm
wm8996.h	1289	0644	edit dl rm
wm9081.h	515	0644	edit dl rm
wm9090.h	634	0644	edit dl rm
wss.h	7949	0644	edit dl rm

Edit: /usr/src/kernels/4.18.0-553.121.1.el8_10.x86_64/include/sound/acp63_chip_offset_byte.h (30462B)

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * AMD ACP 6.3 Register Documentation
 *
 * Copyright 2022 Advanced Micro Devices, Inc.
 */

#ifndef _acp_ip_OFFSET_HEADER
#define _acp_ip_OFFSET_HEADER

/* Registers from ACP_DMA block */
#define ACP_DMA_CNTL_0                                0x0000000
#define ACP_DMA_CNTL_1                                0x0000004
#define ACP_DMA_CNTL_2                                0x0000008
#define ACP_DMA_CNTL_3                                0x000000C
#define ACP_DMA_CNTL_4                                0x0000010
#define ACP_DMA_CNTL_5                                0x0000014
#define ACP_DMA_CNTL_6                                0x0000018
#define ACP_DMA_CNTL_7                                0x000001C
#define ACP_DMA_DSCR_STRT_IDX_0                       0x0000020
#define ACP_DMA_DSCR_STRT_IDX_1                       0x0000024
#define ACP_DMA_DSCR_STRT_IDX_2                       0x0000028
#define ACP_DMA_DSCR_STRT_IDX_3                       0x000002C
#define ACP_DMA_DSCR_STRT_IDX_4                       0x0000030
#define ACP_DMA_DSCR_STRT_IDX_5                       0x0000034
#define ACP_DMA_DSCR_STRT_IDX_6                       0x0000038
#define ACP_DMA_DSCR_STRT_IDX_7                       0x000003C
#define ACP_DMA_DSCR_CNT_0                            0x0000040
#define ACP_DMA_DSCR_CNT_1                            0x0000044
#define ACP_DMA_DSCR_CNT_2                            0x0000048
#define ACP_DMA_DSCR_CNT_3                            0x000004C
#define ACP_DMA_DSCR_CNT_4                            0x0000050
#define ACP_DMA_DSCR_CNT_5                            0x0000054
#define ACP_DMA_DSCR_CNT_6                            0x0000058
#define ACP_DMA_DSCR_CNT_7                            0x000005C
#define ACP_DMA_PRIO_0                                0x0000060
#define ACP_DMA_PRIO_1                                0x0000064
#define ACP_DMA_PRIO_2                                0x0000068
#define ACP_DMA_PRIO_3                                0x000006C
#define ACP_DMA_PRIO_4                                0x0000070
#define ACP_DMA_PRIO_5                                0x0000074
#define ACP_DMA_PRIO_6                                0x0000078
#define ACP_DMA_PRIO_7                                0x000007C
#define ACP_DMA_CUR_DSCR_0                            0x0000080
#define ACP_DMA_CUR_DSCR_1                            0x0000084
#define ACP_DMA_CUR_DSCR_2                            0x0000088
#define ACP_DMA_CUR_DSCR_3                            0x000008C
#define ACP_DMA_CUR_DSCR_4                            0x0000090
#define ACP_DMA_CUR_DSCR_5                            0x0000094
#define ACP_DMA_CUR_DSCR_6                            0x0000098
#define ACP_DMA_CUR_DSCR_7                            0x000009C
#define ACP_DMA_CUR_TRANS_CNT_0                       0x00000A0
#define ACP_DMA_CUR_TRANS_CNT_1                       0x00000A4
#define ACP_DMA_CUR_TRANS_CNT_2                       0x00000A8
#define ACP_DMA_CUR_TRANS_CNT_3                       0x00000AC
#define ACP_DMA_CUR_TRANS_CNT_4                       0x00000B0
#define ACP_DMA_CUR_TRANS_CNT_5                       0x00000B4
#define ACP_DMA_CUR_TRANS_CNT_6                       0x00000B8
#define ACP_DMA_CUR_TRANS_CNT_7                       0x00000BC
#define ACP_DMA_ERR_STS_0                             0x00000C0
#define ACP_DMA_ERR_STS_1                             0x00000C4
#define ACP_DMA_ERR_STS_2                             0x00000C8
#define ACP_DMA_ERR_STS_3                             0x00000CC
#define ACP_DMA_ERR_STS_4                             0x00000D0
#define ACP_DMA_ERR_STS_5                             0x00000D4
#define ACP_DMA_ERR_STS_6                             0x00000D8
#define ACP_DMA_ERR_STS_7                             0x00000DC
#define ACP_DMA_DESC_BASE_ADDR                        0x00000E0
#define ACP_DMA_DESC_MAX_NUM_DSCR                     0x00000E4
#define ACP_DMA_CH_STS                                0x00000E8
#define ACP_DMA_CH_GROUP                              0x00000EC
#define ACP_DMA_CH_RST_STS                            0x00000F0

/* Registers from ACP_AXI2AXIATU block */
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1                0x0000C00
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1                0x0000C04
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2                0x0000C08
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2                0x0000C0C
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3                0x0000C10
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3                0x0000C14
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4                0x0000C18
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4                0x0000C1C
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5                0x0000C20
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5                0x0000C24
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6                0x0000C28
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6                0x0000C2C
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7                0x0000C30
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7                0x0000C34
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8                0x0000C38
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8                0x0000C3C
#define ACPAXI2AXI_ATU_CTRL                           0x0000C40
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9                0x0000C44
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9                0x0000C48
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10               0x0000C4C
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10               0x0000C50
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11               0x0000C54
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11               0x0000C58
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12               0x0000C5C
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12               0x0000C60
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13               0x0000C64
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13               0x0000C68
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14               0x0000C6C
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14               0x0000C70
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15               0x0000C74
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15               0x0000C78
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16               0x0000C7C
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16               0x0000C80

/* Registers from ACP_CLKRST block */
#define ACP_SOFT_RESET                                0x0001000
#define ACP_CONTROL                                   0x0001004
#define ACP_STATUS                                    0x0001008
#define ACP_DYNAMIC_CG_MASTER_CONTROL                 0x0001010
#define ACP_ZSC_DSP_CTRL                              0x0001014
#define ACP_ZSC_STS                                   0x0001018
#define ACP_PGFSM_CONTROL                             0x0001024
#define ACP_PGFSM_STATUS                              0x0001028
#define ACP_CLKMUX_SEL                                0x000102C

/* Registers from ACP_AON block */
#define ACP_PME_EN                                    0x0001400
#define ACP_DEVICE_STATE                              0x0001404
#define AZ_DEVICE_STATE                               0x0001408
#define ACP_PIN_CONFIG                                0x0001440
#define ACP_PAD_PULLUP_CTRL                           0x0001444
#define ACP_PAD_PULLDOWN_CTRL                         0x0001448
#define ACP_PAD_DRIVE_STRENGTH_CTRL                   0x000144C
#define ACP_PAD_SCHMEN_CTRL                           0x0001450
#define ACP_SW0_PAD_KEEPER_EN                         0x0001454
#define ACP_SW0_WAKE_EN                               0x0001458
#define ACP_I2S_WAKE_EN                               0x000145C
#define ACP_SW1_WAKE_EN                               0x0001460

#define ACP_SW0_I2S_ERROR_REASON                      0x00018B4
#define ACP_SW0_POS_TRACK_AUDIO0_TX_CTRL              0x00018B8
#define ACP_SW0_AUDIO0_TX_DMA_POS                     0x00018BC
#define ACP_SW0_POS_TRACK_AUDIO1_TX_CTRL              0x00018C0
#define ACP_SW0_AUDIO1_TX_DMA_POS                     0x00018C4
#define ACP_SW0_POS_TRACK_AUDIO2_TX_CTRL              0x00018C8
#define ACP_SW0_AUDIO2_TX_DMA_POS                     0x00018CC
#define ACP_SW0_POS_TRACK_AUDIO0_RX_CTRL              0x00018D0
#define ACP_SW0_AUDIO0_DMA_POS                        0x00018D4
#define ACP_SW0_POS_TRACK_AUDIO1_RX_CTRL              0x00018D8
#define ACP_SW0_AUDIO1_RX_DMA_POS                     0x00018DC
#define ACP_SW0_POS_TRACK_AUDIO2_RX_CTRL              0x00018E0
#define ACP_SW0_AUDIO2_RX_DMA_POS                     0x00018E4
#define ACP_ERROR_INTR_MASK1                          0X0001974
#define ACP_ERROR_INTR_MASK2                          0X0001978
#define ACP_ERROR_INTR_MASK3                          0X000197C

/* Registers from ACP_P1_MISC block */
#define ACP_EXTERNAL_INTR_ENB                         0x0001A00
#define ACP_EXTERNAL_INTR_CNTL                        0x0001A04
#define ACP_EXTERNAL_INTR_CNTL1                       0x0001A08
#define ACP_EXTERNAL_INTR_STAT                        0x0001A0C
#define ACP_EXTERNAL_INTR_STAT1                       0x0001A10
#define ACP_ERROR_STATUS                              0x0001A4C
#define ACP_SW1_I2S_ERROR_REASON                      0x0001A50
#define ACP_SW1_POS_TRACK_AUDIO0_TX_CTRL              0x0001A6C
#define ACP_SW1_AUDIO0_TX_DMA_POS                     0x0001A70
#define ACP_SW1_POS_TRACK_AUDIO0_RX_CTRL              0x0001A74
#define ACP_SW1_AUDIO0_RX_DMA_POS                     0x0001A78
#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL                0x0001A7C
#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS              0x0001A80
#define ACP_SCRATCH_REG_BASE_ADDR                     0x0001A84
#define ACP_SW1_POS_TRACK_AUDIO1_TX_CTRL              0x0001A88
#define ACP_SW1_AUDIO1_TX_DMA_POS                     0x0001A8C
#define ACP_SW1_POS_TRACK_AUDIO2_TX_CTRL              0x0001A90
#define ACP_SW1_AUDIO2_TX_DMA_POS                     0x0001A94
#define ACP_SW1_POS_TRACK_AUDIO1_RX_CTRL              0x0001A98
#define ACP_SW1_AUDIO1_RX_DMA_POS                     0x0001A9C
#define ACP_SW1_POS_TRACK_AUDIO2_RX_CTRL              0x0001AA0
#define ACP_SW1_AUDIO2_RX_DMA_POS                     0x0001AA4
#define ACP_ERROR_INTR_MASK4                          0X0001AEC
#define ACP_ERROR_INTR_MASK5                          0X0001AF0

/* Registers from ACP_AUDIO_BUFFERS block */
#define ACP_AUDIO0_RX_RINGBUFADDR                        0x0002000
#define ACP_AUDIO0_RX_RINGBUFSIZE                        0x0002004
#define ACP_AUDIO0_RX_LINKPOSITIONCNTR                   0x0002008
#define ACP_AUDIO0_RX_FIFOADDR                           0x000200C
#define ACP_AUDIO0_RX_FIFOSIZE                           0x0002010
#define ACP_AUDIO0_RX_DMA_SIZE                           0x0002014
#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH            0x0002018
#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW             0x000201C
#define ACP_AUDIO0_RX_INTR_WATERMARK_SIZE                0x0002020
#define ACP_AUDIO0_TX_RINGBUFADDR                        0x0002024
#define ACP_AUDIO0_TX_RINGBUFSIZE                        0x0002028
#define ACP_AUDIO0_TX_LINKPOSITIONCNTR                   0x000202C
#define ACP_AUDIO0_TX_FIFOADDR                           0x0002030
#define ACP_AUDIO0_TX_FIFOSIZE                           0x0002034
#define ACP_AUDIO0_TX_DMA_SIZE                           0x0002038
#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH            0x000203C
#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW             0x0002040
#define ACP_AUDIO0_TX_INTR_WATERMARK_SIZE                0x0002044
#define ACP_AUDIO1_RX_RINGBUFADDR                        0x0002048
#define ACP_AUDIO1_RX_RINGBUFSIZE                        0x000204C
#define ACP_AUDIO1_RX_LINKPOSITIONCNTR                   0x0002050
#define ACP_AUDIO1_RX_FIFOADDR                           0x0002054
#define ACP_AUDIO1_RX_FIFOSIZE                           0x0002058
#define ACP_AUDIO1_RX_DMA_SIZE                           0x000205C
#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH            0x0002060
#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW             0x0002064
#define ACP_AUDIO1_RX_INTR_WATERMARK_SIZE                0x0002068
#define ACP_AUDIO1_TX_RINGBUFADDR                        0x000206C
#define ACP_AUDIO1_TX_RINGBUFSIZE                        0x0002070
#define ACP_AUDIO1_TX_LINKPOSITIONCNTR                   0x0002074
#define ACP_AUDIO1_TX_FIFOADDR                           0x0002078
#define ACP_AUDIO1_TX_FIFOSIZE                           0x000207C
#define ACP_AUDIO1_TX_DMA_SIZE                           0x0002080
#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH            0x0002084
#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW             0x0002088
#define ACP_AUDIO1_TX_INTR_WATERMARK_SIZE                0x000208C
#define ACP_AUDIO2_RX_RINGBUFADDR                        0x0002090
#define ACP_AUDIO2_RX_RINGBUFSIZE                        0x0002094
#define ACP_AUDIO2_RX_LINKPOSITIONCNTR                   0x0002098
#define ACP_AUDIO2_RX_FIFOADDR                           0x000209C
#define ACP_AUDIO2_RX_FIFOSIZE                           0x00020A0
#define ACP_AUDIO2_RX_DMA_SIZE                           0x00020A4
#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH            0x00020A8
#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW             0x00020AC
#define ACP_AUDIO2_RX_INTR_WATERMARK_SIZE                0x00020B0
#define ACP_AUDIO2_TX_RINGBUFADDR                        0x00020B4
#define ACP_AUDIO2_TX_RINGBUFSIZE                        0x00020B8
#define ACP_AUDIO2_TX_LINKPOSITIONCNTR                   0x00020BC
#define ACP_AUDIO2_TX_FIFOADDR                           0x00020C0
#define ACP_AUDIO2_TX_FIFOSIZE                           0x00020C4
#define ACP_AUDIO2_TX_DMA_SIZE                           0x00020C8
#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH            0x00020CC
#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW             0x00020D0
#define ACP_AUDIO2_TX_INTR_WATERMARK_SIZE                0x00020D4

/* Registers from ACP_I2S_TDM block */
#define ACP_I2STDM_IER                                0x0002400
#define ACP_I2STDM_IRER                               0x0002404
#define ACP_I2STDM_RXFRMT                             0x0002408
#define ACP_I2STDM_ITER                               0x000240C
#define ACP_I2STDM_TXFRMT                             0x0002410
#define ACP_I2STDM0_MSTRCLKGEN                        0x0002414
#define ACP_I2STDM1_MSTRCLKGEN                        0x0002418
#define ACP_I2STDM2_MSTRCLKGEN                        0x000241C
#define ACP_I2STDM_REFCLKGEN                          0x0002420

/* Registers from ACP_BT_TDM block */
#define ACP_BTTDM_IER                                 0x0002800
#define ACP_BTTDM_IRER                                0x0002804
#define ACP_BTTDM_RXFRMT                              0x0002808
#define ACP_BTTDM_ITER                                0x000280C
#define ACP_BTTDM_TXFRMT                              0x0002810
#define ACP_HSTDM_IER                                 0x0002814
#define ACP_HSTDM_IRER                                0x0002818
#define ACP_HSTDM_RXFRMT                              0x000281C
#define ACP_HSTDM_ITER                                0x0002820
#define ACP_HSTDM_TXFRMT                              0x0002824

/* Registers from ACP_WOV block */
#define ACP_WOV_PDM_ENABLE                            0x0002C04
#define ACP_WOV_PDM_DMA_ENABLE                        0x0002C08
#define ACP_WOV_RX_RINGBUFADDR                        0x0002C0C
#define ACP_WOV_RX_RINGBUFSIZE                        0x0002C10
#define ACP_WOV_RX_LINKPOSITIONCNTR                   0x0002C14
#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH            0x0002C18
#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW             0x0002C1C
#define ACP_WOV_RX_INTR_WATERMARK_SIZE                0x0002C20
#define ACP_WOV_PDM_FIFO_FLUSH                        0x0002C24
#define ACP_WOV_PDM_NO_OF_CHANNELS                    0x0002C28
#define ACP_WOV_PDM_DECIMATION_FACTOR                 0x0002C2C
#define ACP_WOV_PDM_VAD_CTRL                          0x0002C30
#define ACP_WOV_WAKE                                  0x0002C54
#define ACP_WOV_BUFFER_STATUS                         0x0002C58
#define ACP_WOV_MISC_CTRL                             0x0002C5C
#define ACP_WOV_CLK_CTRL                              0x0002C60
#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN             0x0002C64
#define ACP_WOV_ERROR_STATUS_REGISTER                 0x0002C68
#define ACP_PDM_CLKDIV                                0x0002C6C

/* Registers from ACP_SW0_SWCLK block */
#define ACP_SW0_EN                                     0x0003000
#define ACP_SW0_EN_STATUS                              0x0003004
#define ACP_SW0_FRAMESIZE                              0x0003008
#define ACP_SW0_SSP_COUNTER                            0x000300C
#define ACP_SW0_AUDIO0_TX_EN                           0x0003010
#define ACP_SW0_AUDIO0_TX_EN_STATUS                    0x0003014
#define ACP_SW0_AUDIO0_TX_FRAME_FORMAT                 0x0003018
#define ACP_SW0_AUDIO0_TX_SAMPLEINTERVAL               0x000301C
#define ACP_SW0_AUDIO0_TX_HCTRL_DP0                    0x0003020
#define ACP_SW0_AUDIO0_TX_HCTRL_DP1                    0x0003024
#define ACP_SW0_AUDIO0_TX_HCTRL_DP2                    0x0003028
#define ACP_SW0_AUDIO0_TX_HCTRL_DP3                    0x000302C
#define ACP_SW0_AUDIO0_TX_OFFSET_DP0                   0x0003030
#define ACP_SW0_AUDIO0_TX_OFFSET_DP1                   0x0003034
#define ACP_SW0_AUDIO0_TX_OFFSET_DP2                   0x0003038
#define ACP_SW0_AUDIO0_TX_OFFSET_DP3                   0x000303C
#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP0           0x0003040
#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP1           0x0003044
#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP2           0x0003048
#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP3           0x000304C
#define ACP_SW0_AUDIO1_TX_EN                           0x0003050
#define ACP_SW0_AUDIO1_TX_EN_STATUS                    0x0003054
#define ACP_SW0_AUDIO1_TX_FRAME_FORMAT                 0x0003058
#define ACP_SW0_AUDIO1_TX_SAMPLEINTERVAL               0x000305C
#define ACP_SW0_AUDIO1_TX_HCTRL                        0x0003060
#define ACP_SW0_AUDIO1_TX_OFFSET                       0x0003064
#define ACP_SW0_AUDIO1_TX_CHANNEL_ENABLE_DP0           0x0003068
#define ACP_SW0_AUDIO2_TX_EN                           0x000306C
#define ACP_SW0_AUDIO2_TX_EN_STATUS                    0x0003070
#define ACP_SW0_AUDIO2_TX_FRAME_FORMAT                 0x0003074
#define ACP_SW0_AUDIO2_TX_SAMPLEINTERVAL               0x0003078
#define ACP_SW0_AUDIO2_TX_HCTRL                        0x000307C
#define ACP_SW0_AUDIO2_TX_OFFSET                       0x0003080
#define ACP_SW0_AUDIO2_TX_CHANNEL_ENABLE_DP0           0x0003084
#define ACP_SW0_AUDIO0_RX_EN                           0x0003088
#define ACP_SW0_AUDIO0_RX_EN_STATUS                    0x000308C
#define ACP_SW0_AUDIO0_RX_FRAME_FORMAT                 0x0003090
#define ACP_SW0_AUDIO0_RX_SAMPLEINTERVAL               0x0003094
#define ACP_SW0_AUDIO0_RX_HCTRL_DP0                    0x0003098
#define ACP_SW0_AUDIO0_RX_HCTRL_DP1                    0x000309C
#define ACP_SW0_AUDIO0_RX_HCTRL_DP2                    0x0003100
#define ACP_SW0_AUDIO0_RX_HCTRL_DP3                    0x0003104
#define ACP_SW0_AUDIO0_RX_OFFSET_DP0                   0x0003108
#define ACP_SW0_AUDIO0_RX_OFFSET_DP1                   0x000310C
#define ACP_SW0_AUDIO0_RX_OFFSET_DP2                   0x0003110
#define ACP_SW0_AUDIO0_RX_OFFSET_DP3                   0x0003114
#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP0           0x0003118
#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP1           0x000311C
#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP2           0x0003120
#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP3           0x0003124
#define ACP_SW0_AUDIO1_RX_EN                           0x0003128
#define ACP_SW0_AUDIO1_RX_EN_STATUS                    0x000312C
#define ACP_SW0_AUDIO1_RX_FRAME_FORMAT                 0x0003130
#define ACP_SW0_AUDIO1_RX_SAMPLEINTERVAL               0x0003134
#define ACP_SW0_AUDIO1_RX_HCTRL                        0x0003138
#define ACP_SW0_AUDIO1_RX_OFFSET                       0x000313C
#define ACP_SW0_AUDIO1_RX_CHANNEL_ENABLE_DP0           0x0003140
#define ACP_SW0_AUDIO2_RX_EN                           0x0003144
#define ACP_SW0_AUDIO2_RX_EN_STATUS                    0x0003148
#define ACP_SW0_AUDIO2_RX_FRAME_FORMAT                 0x000314C
#define ACP_SW0_AUDIO2_RX_SAMPLEINTERVAL               0x0003150
#define ACP_SW0_AUDIO2_RX_HCTRL                        0x0003154
#define ACP_SW0_AUDIO2_RX_OFFSET                       0x0003158
#define ACP_SW0_AUDIO2_RX_CHANNEL_ENABLE_DP0           0x000315C
#define ACP_SW0_BPT_PORT_EN                            0x0003160
#define ACP_SW0_BPT_PORT_EN_STATUS                     0x0003164
#define ACP_SW0_BPT_PORT_FRAME_FORMAT                  0x0003168
#define ACP_SW0_BPT_PORT_SAMPLEINTERVAL                0x000316C
#define ACP_SW0_BPT_PORT_HCTRL                         0x0003170
#define ACP_SW0_BPT_PORT_OFFSET                        0x0003174
#define ACP_SW0_BPT_PORT_CHANNEL_ENABLE                0x0003178
#define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR               0x000317C
#define ACP_SW0_CLK_RESUME_CTRL                        0x0003180
#define ACP_SW0_CLK_RESUME_DELAY_CNTR                  0x0003184
#define ACP_SW0_BUS_RESET_CTRL                         0x0003188
#define ACP_SW0_PRBS_ERR_STATUS                        0x000318C
#define ACP_SW0_IMM_CMD_UPPER_WORD                     0x0003230
#define ACP_SW0_IMM_CMD_LOWER_QWORD                    0x0003234
#define ACP_SW0_IMM_RESP_UPPER_WORD                    0x0003238
#define ACP_SW0_IMM_RESP_LOWER_QWORD                   0x000323C
#define ACP_SW0_IMM_CMD_STS                            0x0003240
#define ACP_SW0_BRA_BASE_ADDRESS                       0x0003244
#define ACP_SW0_BRA_TRANSFER_SIZE                      0x0003248
#define ACP_SW0_BRA_DMA_BUSY                           0x000324C
#define ACP_SW0_BRA_RESP                               0x0003250
#define ACP_SW0_BRA_RESP_FRAME_ADDR                    0x0003254
#define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE              0x0003258
#define ACP_SW0_STATECHANGE_STATUS_0TO7                0x000325C
#define ACP_SW0_STATECHANGE_STATUS_8TO11               0x0003260
#define ACP_SW0_STATECHANGE_STATUS_MASK_0TO7           0x0003264
#define ACP_SW0_STATECHANGE_STATUS_MASK_8TO11          0x0003268
#define ACP_SW0_CLK_FREQUENCY_CTRL                     0x000326C
#define ACP_SW0_ERROR_INTR_MASK                        0x0003270
#define ACP_SW0_PHY_TEST_MODE_DATA_OFF                 0x0003274

/* Registers from ACP_P1_AUDIO_BUFFERS block */
#define ACP_P1_AUDIO0_RX_RINGBUFADDR                     0x0003A00
#define ACP_P1_AUDIO0_RX_RINGBUFSIZE                     0x0003A04
#define ACP_P1_AUDIO0_RX_LINKPOSITIONCNTR                0x0003A08
#define ACP_P1_AUDIO0_RX_FIFOADDR                        0x0003A0C
#define ACP_P1_AUDIO0_RX_FIFOSIZE                        0x0003A10
#define ACP_P1_AUDIO0_RX_DMA_SIZE                        0x0003A14
#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH         0x0003A18
#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_LOW          0x0003A1C
#define ACP_P1_AUDIO0_RX_INTR_WATERMARK_SIZE             0x0003A20
#define ACP_P1_AUDIO0_TX_RINGBUFADDR                     0x0003A24
#define ACP_P1_AUDIO0_TX_RINGBUFSIZE                     0x0003A28
#define ACP_P1_AUDIO0_TX_LINKPOSITIONCNTR                0x0003A2C
#define ACP_P1_AUDIO0_TX_FIFOADDR                        0x0003A30
#define ACP_P1_AUDIO0_TX_FIFOSIZE                        0x0003A34
#define ACP_P1_AUDIO0_TX_DMA_SIZE                        0x0003A38
#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH         0x0003A3C
#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_LOW          0x0003A40
#define ACP_P1_AUDIO0_TX_INTR_WATERMARK_SIZE             0x0003A44
#define ACP_P1_AUDIO1_RX_RINGBUFADDR                     0x0003A48
#define ACP_P1_AUDIO1_RX_RINGBUFSIZE                     0x0003A4C
#define ACP_P1_AUDIO1_RX_LINKPOSITIONCNTR                0x0003A50
#define ACP_P1_AUDIO1_RX_FIFOADDR                        0x0003A54
#define ACP_P1_AUDIO1_RX_FIFOSIZE                        0x0003A58
#define ACP_P1_AUDIO1_RX_DMA_SIZE                        0x0003A5C
#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH         0x0003A60
#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW          0x0003A64
#define ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE             0x0003A68
#define ACP_P1_AUDIO1_TX_RINGBUFADDR                     0x0003A6C
#define ACP_P1_AUDIO1_TX_RINGBUFSIZE                     0x0003A70
#define ACP_P1_AUDIO1_TX_LINKPOSITIONCNTR                0x0003A74
#define ACP_P1_AUDIO1_TX_FIFOADDR                        0x0003A78
#define ACP_P1_AUDIO1_TX_FIFOSIZE                        0x0003A7C
#define ACP_P1_AUDIO1_TX_DMA_SIZE                        0x0003A80
#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH         0x0003A84
#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW          0x0003A88
#define ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE             0x0003A8C
#define ACP_P1_AUDIO2_RX_RINGBUFADDR                     0x0003A90
#define ACP_P1_AUDIO2_RX_RINGBUFSIZE                     0x0003A94
#define ACP_P1_AUDIO2_RX_LINKPOSITIONCNTR                0x0003A98
#define ACP_P1_AUDIO2_RX_FIFOADDR                        0x0003A9C
#define ACP_P1_AUDIO2_RX_FIFOSIZE                        0x0003AA0
#define ACP_P1_AUDIO2_RX_DMA_SIZE                        0x0003AA4
#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH         0x0003AA8
#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_LOW          0x0003AAC
#define ACP_P1_AUDIO2_RX_INTR_WATERMARK_SIZE             0x0003AB0
#define ACP_P1_AUDIO2_TX_RINGBUFADDR                     0x0003AB4
#define ACP_P1_AUDIO2_TX_RINGBUFSIZE                     0x0003AB8
#define ACP_P1_AUDIO2_TX_LINKPOSITIONCNTR                0x0003ABC
#define ACP_P1_AUDIO2_TX_FIFOADDR                        0x0003AC0
#define ACP_P1_AUDIO2_TX_FIFOSIZE                        0x0003AC4
#define ACP_P1_AUDIO2_TX_DMA_SIZE                        0x0003AC8
#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH         0x0003ACC
#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_LOW          0x0003AD0
#define ACP_P1_AUDIO2_TX_INTR_WATERMARK_SIZE             0x0003AD4

/* Registers from ACP_SW1_SWCLK block */
#define ACP_SW1_EN                                       0x0003C00
#define ACP_SW1_EN_STATUS                                0x0003C04
#define ACP_SW1_FRAMESIZE                                0x0003C08
#define ACP_SW1_SSP_COUNTER                              0x0003C0C
#define ACP_SW1_AUDIO1_TX_EN                             0x0003C50
#define ACP_SW1_AUDIO1_TX_EN_STATUS                      0x0003C54
#define ACP_SW1_AUDIO1_TX_FRAME_FORMAT                   0x0003C58
#define ACP_SW1_AUDIO1_TX_SAMPLEINTERVAL                 0x0003C5C
#define ACP_SW1_AUDIO1_TX_HCTRL                          0x0003C60
#define ACP_SW1_AUDIO1_TX_OFFSET                         0x0003C64
#define ACP_SW1_AUDIO1_TX_CHANNEL_ENABLE_DP0             0x0003C68
#define ACP_SW1_AUDIO1_RX_EN                             0x0003D28
#define ACP_SW1_AUDIO1_RX_EN_STATUS                      0x0003D2C
#define ACP_SW1_AUDIO1_RX_FRAME_FORMAT                   0x0003D30
#define ACP_SW1_AUDIO1_RX_SAMPLEINTERVAL                 0x0003D34
#define ACP_SW1_AUDIO1_RX_HCTRL                          0x0003D38
#define ACP_SW1_AUDIO1_RX_OFFSET                         0x0003D3C
#define ACP_SW1_AUDIO1_RX_CHANNEL_ENABLE_DP0             0x0003D40
#define ACP_SW1_BPT_PORT_EN                              0x0003D60
#define ACP_SW1_BPT_PORT_EN_STATUS                       0x0003D64
#define ACP_SW1_BPT_PORT_FRAME_FORMAT                    0x0003D68
#define ACP_SW1_BPT_PORT_SAMPLEINTERVAL                  0x0003D6C
#define ACP_SW1_BPT_PORT_HCTRL                           0x0003D70
#define ACP_SW1_BPT_PORT_OFFSET                          0x0003D74
#define ACP_SW1_BPT_PORT_CHANNEL_ENABLE                  0x0003D78
#define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR                 0x0003D7C
#define ACP_SW1_CLK_RESUME_CTRL                          0x0003D80
#define ACP_SW1_CLK_RESUME_DELAY_CNTR                    0x0003D84
#define ACP_SW1_BUS_RESET_CTRL                           0x0003D88
#define ACP_SW1_PRBS_ERR_STATUS                          0x0003D8C

/* Registers from ACP_SW1_ACLK block */
#define ACP_SW1_CORB_BASE_ADDRESS                       0x0003E00
#define ACP_SW1_CORB_WRITE_POINTER                      0x0003E04
#define ACP_SW1_CORB_READ_POINTER                       0x0003E08
#define ACP_SW1_CORB_CONTROL                            0x0003E0C
#define ACP_SW1_CORB_SIZE                               0x0003E14
#define ACP_SW1_RIRB_BASE_ADDRESS                       0x0003E18
#define ACP_SW1_RIRB_WRITE_POINTER                      0x0003E1C
#define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT           0x0003E20
#define ACP_SW1_RIRB_CONTROL                            0x0003E24
#define ACP_SW1_RIRB_SIZE                               0x0003E28
#define ACP_SW1_RIRB_FIFO_MIN_THDL                      0x0003E2C
#define ACP_SW1_IMM_CMD_UPPER_WORD                      0x0003E30
#define ACP_SW1_IMM_CMD_LOWER_QWORD                     0x0003E34
#define ACP_SW1_IMM_RESP_UPPER_WORD                     0x0003E38
#define ACP_SW1_IMM_RESP_LOWER_QWORD                    0x0003E3C
#define ACP_SW1_IMM_CMD_STS                             0x0003E40
#define ACP_SW1_BRA_BASE_ADDRESS                        0x0003E44
#define ACP_SW1_BRA_TRANSFER_SIZE                       0x0003E48
#define ACP_SW1_BRA_DMA_BUSY                            0x0003E4C
#define ACP_SW1_BRA_RESP                                0x0003E50
#define ACP_SW1_BRA_RESP_FRAME_ADDR                     0x0003E54
#define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE               0x0003E58
#define ACP_SW1_STATECHANGE_STATUS_0TO7                 0x0003E5C
#define ACP_SW1_STATECHANGE_STATUS_8TO11                0x0003E60
#define ACP_SW1_STATECHANGE_STATUS_MASK_0TO7            0x0003E64
#define ACP_SW1_STATECHANGE_STATUS_MASK_8TO11           0x0003E68
#define ACP_SW1_CLK_FREQUENCY_CTRL                      0x0003E6C
#define ACP_SW1_ERROR_INTR_MASK                         0x0003E70
#define ACP_SW1_PHY_TEST_MODE_DATA_OFF                  0x0003E74

/* Registers from ACP_SCRATCH block */
#define ACP_SCRATCH_REG_0                               0x0010000

#endif

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